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Update memtest results due to new deferred-target-promotion fix.

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Turned out this scenario was happening, but due to other activity,
the writable block returned by the ReadResp would get downgraded
or invalidated before the "unnecessary" ReadExResp/UpgradeResp
returned, thus avoiding triggering the assertion that led us to
catch this.

--HG--
extra : convert_revision : 19dd0dbedb0227aed29da31a868ddf5ca4c50519
This commit is contained in:
Steve Reinhardt 2007-11-16 20:10:33 -08:00
parent 7d83cf35e1
commit 21a99af009
3 changed files with 517 additions and 517 deletions
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992
tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
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File diff suppressed because it is too large Load diff

34
tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
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@ -55,20 +55,20 @@ system.cpu1: completed 70000 read accesses @114429712
system.cpu0: completed 70000 read accesses @114626666
system.cpu4: completed 70000 read accesses @115046863
system.cpu6: completed 70000 read accesses @115625699
system.cpu7: completed 80000 read accesses @130041792
system.cpu5: completed 80000 read accesses @130054396
system.cpu1: completed 80000 read accesses @130640538
system.cpu3: completed 80000 read accesses @130746631
system.cpu0: completed 80000 read accesses @130757460
system.cpu2: completed 80000 read accesses @130848004
system.cpu4: completed 80000 read accesses @131798404
system.cpu6: completed 80000 read accesses @132427801
system.cpu7: completed 90000 read accesses @146399168
system.cpu3: completed 90000 read accesses @146528404
system.cpu0: completed 90000 read accesses @146893614
system.cpu5: completed 90000 read accesses @147004410
system.cpu1: completed 90000 read accesses @147082543
system.cpu2: completed 90000 read accesses @147344874
system.cpu4: completed 90000 read accesses @148040578
system.cpu6: completed 90000 read accesses @149090244
system.cpu7: completed 100000 read accesses @163028791
system.cpu7: completed 80000 read accesses @130114471
system.cpu5: completed 80000 read accesses @130239115
system.cpu3: completed 80000 read accesses @130679996
system.cpu1: completed 80000 read accesses @130860729
system.cpu0: completed 80000 read accesses @131170286
system.cpu2: completed 80000 read accesses @131219347
system.cpu4: completed 80000 read accesses @131694972
system.cpu6: completed 80000 read accesses @132127278
system.cpu7: completed 90000 read accesses @146355152
system.cpu5: completed 90000 read accesses @146631518
system.cpu3: completed 90000 read accesses @146856424
system.cpu1: completed 90000 read accesses @147217275
system.cpu0: completed 90000 read accesses @147658368
system.cpu2: completed 90000 read accesses @147775118
system.cpu4: completed 90000 read accesses @148157312
system.cpu6: completed 90000 read accesses @148500053
system.cpu5: completed 100000 read accesses @162969030

8
tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 12 2007 00:26:55
M5 started Sun Aug 12 12:13:31 2007
M5 executing on zeep
M5 compiled Nov 13 2007 20:22:15
M5 started Tue Nov 13 20:22:26 2007
M5 executing on vm1
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 163028791 because maximum number of loads reached
Exiting @ tick 162969030 because maximum number of loads reached