Update memtest results due to new deferred-target-promotion fix.
Turned out this scenario was happening, but due to other activity, the writable block returned by the ReadResp would get downgraded or invalidated before the "unnecessary" ReadExResp/UpgradeResp returned, thus avoiding triggering the assertion that led us to catch this. --HG-- extra : convert_revision : 19dd0dbedb0227aed29da31a868ddf5ca4c50519
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@ -55,20 +55,20 @@ system.cpu1: completed 70000 read accesses @114429712
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system.cpu0: completed 70000 read accesses @114626666
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system.cpu0: completed 70000 read accesses @114626666
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system.cpu4: completed 70000 read accesses @115046863
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system.cpu4: completed 70000 read accesses @115046863
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system.cpu6: completed 70000 read accesses @115625699
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system.cpu6: completed 70000 read accesses @115625699
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system.cpu7: completed 80000 read accesses @130041792
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system.cpu7: completed 80000 read accesses @130114471
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system.cpu5: completed 80000 read accesses @130054396
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system.cpu5: completed 80000 read accesses @130239115
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system.cpu1: completed 80000 read accesses @130640538
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system.cpu3: completed 80000 read accesses @130679996
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system.cpu3: completed 80000 read accesses @130746631
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system.cpu1: completed 80000 read accesses @130860729
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system.cpu0: completed 80000 read accesses @130757460
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system.cpu0: completed 80000 read accesses @131170286
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system.cpu2: completed 80000 read accesses @130848004
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system.cpu2: completed 80000 read accesses @131219347
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system.cpu4: completed 80000 read accesses @131798404
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system.cpu4: completed 80000 read accesses @131694972
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system.cpu6: completed 80000 read accesses @132427801
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system.cpu6: completed 80000 read accesses @132127278
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system.cpu7: completed 90000 read accesses @146399168
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system.cpu7: completed 90000 read accesses @146355152
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system.cpu3: completed 90000 read accesses @146528404
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system.cpu5: completed 90000 read accesses @146631518
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system.cpu0: completed 90000 read accesses @146893614
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system.cpu3: completed 90000 read accesses @146856424
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system.cpu5: completed 90000 read accesses @147004410
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system.cpu1: completed 90000 read accesses @147217275
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system.cpu1: completed 90000 read accesses @147082543
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system.cpu0: completed 90000 read accesses @147658368
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system.cpu2: completed 90000 read accesses @147344874
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system.cpu2: completed 90000 read accesses @147775118
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system.cpu4: completed 90000 read accesses @148040578
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system.cpu4: completed 90000 read accesses @148157312
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system.cpu6: completed 90000 read accesses @149090244
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system.cpu6: completed 90000 read accesses @148500053
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system.cpu7: completed 100000 read accesses @163028791
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system.cpu5: completed 100000 read accesses @162969030
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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All Rights Reserved
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M5 compiled Aug 12 2007 00:26:55
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M5 compiled Nov 13 2007 20:22:15
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M5 started Sun Aug 12 12:13:31 2007
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M5 started Tue Nov 13 20:22:26 2007
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M5 executing on zeep
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M5 executing on vm1
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
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Global frequency set at 1000000000000 ticks per second
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Global frequency set at 1000000000000 ticks per second
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Exiting @ tick 163028791 because maximum number of loads reached
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Exiting @ tick 162969030 because maximum number of loads reached
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