cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful. Specifically, made these substitutions: s/FP_Base_DepTag/FP_Reg_Base/g; s/Ctrl_Base_DepTag/Misc_Reg_Base/g; s/Max_DepTag/Max_Reg_Index/g;
This commit is contained in:
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a830e63de7
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219c423f1f
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@ -149,7 +149,7 @@ output decoder {{
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#ifndef SS_COMPATIBLE_DISASSEMBLY
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#ifndef SS_COMPATIBLE_DISASSEMBLY
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std::string suffix("");
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std::string suffix("");
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suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
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suffix += ((_destRegIdx[0] >= FP_Reg_Base)
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? fpTrappingModeSuffix[trappingMode]
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? fpTrappingModeSuffix[trappingMode]
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: intTrappingModeSuffix[trappingMode]);
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: intTrappingModeSuffix[trappingMode]);
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suffix += roundingModeSuffix[roundingMode];
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suffix += roundingModeSuffix[roundingMode];
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@ -224,7 +224,7 @@ output header {{
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/// this class and derived classes. Maybe these should really
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/// this class and derived classes. Maybe these should really
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/// live here and not in the AlphaISA namespace.
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/// live here and not in the AlphaISA namespace.
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enum DependenceTags {
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enum DependenceTags {
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FP_Base_DepTag = AlphaISA::FP_Base_DepTag
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FP_Reg_Base = AlphaISA::FP_Reg_Base
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};
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};
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/// Constructor.
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/// Constructor.
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@ -253,11 +253,11 @@ output decoder {{
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void
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void
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AlphaStaticInst::printReg(std::ostream &os, int reg) const
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AlphaStaticInst::printReg(std::ostream &os, int reg) const
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{
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{
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if (reg < FP_Base_DepTag) {
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if (reg < FP_Reg_Base) {
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ccprintf(os, "r%d", reg);
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ccprintf(os, "r%d", reg);
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}
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}
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else {
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else {
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ccprintf(os, "f%d", reg - FP_Base_DepTag);
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ccprintf(os, "f%d", reg - FP_Reg_Base);
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}
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}
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}
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}
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@ -99,10 +99,10 @@ const int TotalNumRegs =
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// These enumerate all the registers for dependence tracking.
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// These enumerate all the registers for dependence tracking.
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enum DependenceTags {
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enum DependenceTags {
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// 0..31 are the integer regs 0..31
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// 0..31 are the integer regs 0..31
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// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
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// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
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FP_Base_DepTag = NumIntRegs,
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FP_Reg_Base = NumIntRegs,
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Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
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Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
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Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs + NumInternalProcRegs
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Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
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};
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};
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} // namespace AlphaISA
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} // namespace AlphaISA
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@ -80,10 +80,10 @@ MsrBase::printMsrBase(std::ostream &os) const
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bool foundPsr = false;
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bool foundPsr = false;
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for (unsigned i = 0; i < numDestRegs(); i++) {
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for (unsigned i = 0; i < numDestRegs(); i++) {
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int idx = destRegIdx(i);
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int idx = destRegIdx(i);
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if (idx < Ctrl_Base_DepTag) {
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if (idx < Misc_Reg_Base) {
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continue;
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continue;
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}
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}
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idx -= Ctrl_Base_DepTag;
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idx -= Misc_Reg_Base;
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if (idx == MISCREG_CPSR) {
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if (idx == MISCREG_CPSR) {
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os << "cpsr_";
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os << "cpsr_";
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foundPsr = true;
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foundPsr = true;
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@ -50,9 +50,9 @@ FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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{
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std::stringstream ss;
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std::stringstream ss;
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printMnemonic(ss);
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printMnemonic(ss);
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printReg(ss, dest + FP_Base_DepTag);
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printReg(ss, dest + FP_Reg_Base);
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ss << ", ";
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ss << ", ";
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printReg(ss, op1 + FP_Base_DepTag);
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printReg(ss, op1 + FP_Reg_Base);
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return ss.str();
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return ss.str();
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}
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}
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@ -61,7 +61,7 @@ FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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{
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std::stringstream ss;
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std::stringstream ss;
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printMnemonic(ss);
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printMnemonic(ss);
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printReg(ss, dest + FP_Base_DepTag);
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printReg(ss, dest + FP_Reg_Base);
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ccprintf(ss, ", #%d", imm);
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ccprintf(ss, ", #%d", imm);
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return ss.str();
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return ss.str();
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}
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}
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@ -71,9 +71,9 @@ FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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{
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std::stringstream ss;
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std::stringstream ss;
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printMnemonic(ss);
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printMnemonic(ss);
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printReg(ss, dest + FP_Base_DepTag);
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printReg(ss, dest + FP_Reg_Base);
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ss << ", ";
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ss << ", ";
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printReg(ss, op1 + FP_Base_DepTag);
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printReg(ss, op1 + FP_Reg_Base);
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ccprintf(ss, ", #%d", imm);
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ccprintf(ss, ", #%d", imm);
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return ss.str();
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return ss.str();
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}
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}
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@ -83,11 +83,11 @@ FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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{
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std::stringstream ss;
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std::stringstream ss;
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printMnemonic(ss);
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printMnemonic(ss);
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printReg(ss, dest + FP_Base_DepTag);
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printReg(ss, dest + FP_Reg_Base);
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ss << ", ";
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ss << ", ";
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printReg(ss, op1 + FP_Base_DepTag);
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printReg(ss, op1 + FP_Reg_Base);
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ss << ", ";
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ss << ", ";
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printReg(ss, op2 + FP_Base_DepTag);
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printReg(ss, op2 + FP_Reg_Base);
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return ss.str();
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return ss.str();
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}
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}
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@ -96,11 +96,11 @@ FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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{
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std::stringstream ss;
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std::stringstream ss;
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printMnemonic(ss);
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printMnemonic(ss);
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printReg(ss, dest + FP_Base_DepTag);
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printReg(ss, dest + FP_Reg_Base);
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ss << ", ";
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ss << ", ";
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printReg(ss, op1 + FP_Base_DepTag);
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printReg(ss, op1 + FP_Reg_Base);
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ss << ", ";
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ss << ", ";
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printReg(ss, op2 + FP_Base_DepTag);
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printReg(ss, op2 + FP_Reg_Base);
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ccprintf(ss, ", #%d", imm);
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ccprintf(ss, ", #%d", imm);
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return ss.str();
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return ss.str();
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}
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}
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@ -101,9 +101,9 @@ const int SyscallPseudoReturnReg = ReturnValueReg;
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const int SyscallSuccessReg = ReturnValueReg;
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const int SyscallSuccessReg = ReturnValueReg;
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// These help enumerate all the registers for dependence tracking.
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// These help enumerate all the registers for dependence tracking.
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const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
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const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
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const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
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const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
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const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
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const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
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typedef union {
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typedef union {
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IntReg intreg;
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IntReg intreg;
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@ -610,12 +610,12 @@ class FloatRegOperand(Operand):
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c_dest = ''
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c_dest = ''
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if self.is_src:
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if self.is_src:
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c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Base_DepTag;' % \
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c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Reg_Base;' % \
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(self.reg_spec)
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(self.reg_spec)
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if self.is_dest:
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if self.is_dest:
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c_dest = \
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c_dest = \
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'\n\t_destRegIdx[_numDestRegs++] = %s + FP_Base_DepTag;' % \
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'\n\t_destRegIdx[_numDestRegs++] = %s + FP_Reg_Base;' % \
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(self.reg_spec)
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(self.reg_spec)
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c_dest += '\n\t_numFPDestRegs++;'
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c_dest += '\n\t_numFPDestRegs++;'
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if self.is_src:
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if self.is_src:
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c_src = \
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c_src = \
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'\n\t_srcRegIdx[_numSrcRegs++] = %s + Ctrl_Base_DepTag;' % \
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'\n\t_srcRegIdx[_numSrcRegs++] = %s + Misc_Reg_Base;' % \
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(self.reg_spec)
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(self.reg_spec)
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if self.is_dest:
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if self.is_dest:
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c_dest = \
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c_dest = \
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'\n\t_destRegIdx[_numDestRegs++] = %s + Ctrl_Base_DepTag;' % \
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'\n\t_destRegIdx[_numDestRegs++] = %s + Misc_Reg_Base;' % \
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(self.reg_spec)
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(self.reg_spec)
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return c_src + c_dest
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return c_src + c_dest
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@ -72,11 +72,11 @@ output decoder {{
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void MipsStaticInst::printReg(std::ostream &os, int reg) const
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void MipsStaticInst::printReg(std::ostream &os, int reg) const
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{
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{
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if (reg < FP_Base_DepTag) {
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if (reg < FP_Reg_Base) {
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ccprintf(os, "r%d", reg);
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ccprintf(os, "r%d", reg);
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}
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}
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else {
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else {
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ccprintf(os, "f%d", reg - FP_Base_DepTag);
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ccprintf(os, "f%d", reg - FP_Reg_Base);
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}
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}
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}
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}
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@ -385,7 +385,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x8: decode MT_U {
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0x8: decode MT_U {
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0x0: mftc0({{
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0x0: mftc0({{
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data = xc->readRegOtherThread((RT << 3 | SEL) +
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data = xc->readRegOtherThread((RT << 3 | SEL) +
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Ctrl_Base_DepTag);
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Misc_Reg_Base);
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}});
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}});
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0x1: decode SEL {
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0x1: decode SEL {
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0x0: mftgpr({{
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0x0: mftgpr({{
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}
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}
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0x2: decode MT_H {
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0x2: decode MT_H {
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0x0: mftc1({{ data = xc->readRegOtherThread(RT +
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0x0: mftc1({{ data = xc->readRegOtherThread(RT +
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FP_Base_DepTag);
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FP_Reg_Base);
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}});
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}});
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0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
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0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
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FP_Base_DepTag);
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FP_Reg_Base);
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}});
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}});
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}
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}
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0x3: cftc1({{
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0x3: cftc1({{
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uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
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uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
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FP_Base_DepTag);
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FP_Reg_Base);
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switch (RT) {
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switch (RT) {
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case 0:
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case 0:
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data = xc->readRegOtherThread(FLOATREG_FIR +
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data = xc->readRegOtherThread(FLOATREG_FIR +
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Ctrl_Base_DepTag);
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Misc_Reg_Base);
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break;
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break;
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case 25:
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case 25:
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data = (fcsr_val & 0xFE000000 >> 24) |
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data = (fcsr_val & 0xFE000000 >> 24) |
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format MT_MTTR {
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format MT_MTTR {
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// Decode MIPS MT MTTR instruction into sub-instructions
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// Decode MIPS MT MTTR instruction into sub-instructions
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0xC: decode MT_U {
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0xC: decode MT_U {
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0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
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0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base,
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Rt);
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Rt);
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}});
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}});
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0x1: decode SEL {
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0x1: decode SEL {
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}
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}
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0x2: mttc1({{
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0x2: mttc1({{
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uint64_t data = xc->readRegOtherThread(RD +
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uint64_t data = xc->readRegOtherThread(RD +
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FP_Base_DepTag);
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FP_Reg_Base);
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data = insertBits(data, MT_H ? 63 : 31,
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data = insertBits(data, MT_H ? 63 : 31,
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MT_H ? 32 : 0, Rt);
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MT_H ? 32 : 0, Rt);
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xc->setRegOtherThread(RD + FP_Base_DepTag,
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xc->setRegOtherThread(RD + FP_Reg_Base,
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data);
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data);
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}});
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}});
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0x3: cttc1({{
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0x3: cttc1({{
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"Access to Floating Control "
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"Access to Floating Control "
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"S""tatus Register", FS);
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"S""tatus Register", FS);
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}
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}
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xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
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xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data);
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}});
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}});
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default: CP0Unimpl::unknown();
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default: CP0Unimpl::unknown();
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}
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}
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@ -102,7 +102,7 @@ output exec {{
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MVPConf0Reg &mvp_conf0)
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MVPConf0Reg &mvp_conf0)
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{
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{
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vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
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vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
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tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag);
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tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base);
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tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
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tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
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vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
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vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
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mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
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mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
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@ -113,23 +113,23 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
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int success = 0;
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int success = 0;
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for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
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for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
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TCBindReg tidTCBind =
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TCBindReg tidTCBind =
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tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag, tid);
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tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid);
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TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
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TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
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if (tidTCBind.curVPE == tcBind.curVPE) {
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if (tidTCBind.curVPE == tcBind.curVPE) {
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TCStatusReg tidTCStatus =
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TCStatusReg tidTCStatus =
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tc->readRegOtherThread(MISCREG_TC_STATUS +
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tc->readRegOtherThread(MISCREG_TC_STATUS +
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Ctrl_Base_DepTag,tid);
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Misc_Reg_Base,tid);
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TCHaltReg tidTCHalt =
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TCHaltReg tidTCHalt =
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tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,tid);
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tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,tid);
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if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
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if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
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tidTCStatus.a == 0 && success == 0) {
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tidTCStatus.a == 0 && success == 0) {
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tc->setRegOtherThread(MISCREG_TC_RESTART +
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tc->setRegOtherThread(MISCREG_TC_RESTART +
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Ctrl_Base_DepTag, Rs, tid);
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Misc_Reg_Base, Rs, tid);
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tc->setRegOtherThread(Rd_bits, Rt, tid);
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tc->setRegOtherThread(Rd_bits, Rt, tid);
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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@ -149,7 +149,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
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tidTCStatus.asid = tcStatus.asid;
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tidTCStatus.asid = tcStatus.asid;
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// Write Status Register
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// Write Status Register
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tc->setRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
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tc->setRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
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tidTCStatus, tid);
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tidTCStatus, tid);
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// Mark As Successful Fork
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// Mark As Successful Fork
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||||||
|
@ -185,13 +185,13 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
|
||||||
|
|
||||||
for (ThreadID tid = 0; tid < num_threads; tid++) {
|
for (ThreadID tid = 0; tid < num_threads; tid++) {
|
||||||
TCStatusReg tidTCStatus =
|
TCStatusReg tidTCStatus =
|
||||||
tc->readRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
|
tc->readRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
|
||||||
tid);
|
tid);
|
||||||
TCHaltReg tidTCHalt =
|
TCHaltReg tidTCHalt =
|
||||||
tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,
|
tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,
|
||||||
tid);
|
tid);
|
||||||
TCBindReg tidTCBind =
|
TCBindReg tidTCBind =
|
||||||
tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag,
|
tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base,
|
||||||
tid);
|
tid);
|
||||||
|
|
||||||
if (tidTCBind.curVPE == tcBind.curVPE &&
|
if (tidTCBind.curVPE == tcBind.curVPE &&
|
||||||
|
|
|
@ -275,9 +275,9 @@ enum MiscRegIndex{
|
||||||
const int NumMiscRegs = MISCREG_NUMREGS;
|
const int NumMiscRegs = MISCREG_NUMREGS;
|
||||||
|
|
||||||
// These help enumerate all the registers for dependence tracking.
|
// These help enumerate all the registers for dependence tracking.
|
||||||
const int FP_Base_DepTag = NumIntRegs;
|
const int FP_Reg_Base = NumIntRegs;
|
||||||
const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
|
const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
|
||||||
const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
|
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
|
||||||
|
|
||||||
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
|
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
|
||||||
|
|
||||||
|
|
|
@ -84,9 +84,9 @@ const int SyscallPseudoReturnReg = 3;
|
||||||
const int SyscallSuccessReg = 3;
|
const int SyscallSuccessReg = 3;
|
||||||
|
|
||||||
// These help enumerate all the registers for dependence tracking.
|
// These help enumerate all the registers for dependence tracking.
|
||||||
const int FP_Base_DepTag = NumIntRegs;
|
const int FP_Reg_Base = NumIntRegs;
|
||||||
const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
|
const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
|
||||||
const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
|
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
|
||||||
|
|
||||||
typedef union {
|
typedef union {
|
||||||
IntReg intreg;
|
IntReg intreg;
|
||||||
|
|
|
@ -290,7 +290,7 @@ output decoder {{
|
||||||
const int MaxLocal = 24;
|
const int MaxLocal = 24;
|
||||||
const int MaxInput = 32;
|
const int MaxInput = 32;
|
||||||
const int MaxMicroReg = 40;
|
const int MaxMicroReg = 40;
|
||||||
if (reg < FP_Base_DepTag) {
|
if (reg < FP_Reg_Base) {
|
||||||
// If we used a register from the next or previous window,
|
// If we used a register from the next or previous window,
|
||||||
// take out the offset.
|
// take out the offset.
|
||||||
while (reg >= MaxMicroReg)
|
while (reg >= MaxMicroReg)
|
||||||
|
@ -335,10 +335,10 @@ output decoder {{
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} else if (reg < Ctrl_Base_DepTag) {
|
} else if (reg < Misc_Reg_Base) {
|
||||||
ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
|
ccprintf(os, "%%f%d", reg - FP_Reg_Base);
|
||||||
} else {
|
} else {
|
||||||
switch (reg - Ctrl_Base_DepTag) {
|
switch (reg - Misc_Reg_Base) {
|
||||||
case MISCREG_ASI:
|
case MISCREG_ASI:
|
||||||
ccprintf(os, "%%asi");
|
ccprintf(os, "%%asi");
|
||||||
break;
|
break;
|
||||||
|
@ -430,7 +430,7 @@ output decoder {{
|
||||||
ccprintf(os, "%%fsr");
|
ccprintf(os, "%%fsr");
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
|
ccprintf(os, "%%ctrl%d", reg - Misc_Reg_Base);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -75,9 +75,9 @@ const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
|
||||||
|
|
||||||
// These enumerate all the registers for dependence tracking.
|
// These enumerate all the registers for dependence tracking.
|
||||||
enum DependenceTags {
|
enum DependenceTags {
|
||||||
FP_Base_DepTag = NumIntRegs,
|
FP_Reg_Base = NumIntRegs,
|
||||||
Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
|
Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
|
||||||
Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
|
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
|
||||||
};
|
};
|
||||||
|
|
||||||
} // namespace SparcISA
|
} // namespace SparcISA
|
||||||
|
|
|
@ -65,12 +65,12 @@ const int NumFloatRegs =
|
||||||
|
|
||||||
// These enumerate all the registers for dependence tracking.
|
// These enumerate all the registers for dependence tracking.
|
||||||
enum DependenceTags {
|
enum DependenceTags {
|
||||||
// FP_Base_DepTag must be large enough to be bigger than any integer
|
// FP_Reg_Base must be large enough to be bigger than any integer
|
||||||
// register index which has the IntFoldBit (1 << 6) set. To be safe
|
// register index which has the IntFoldBit (1 << 6) set. To be safe
|
||||||
// we just start at (1 << 7) == 128.
|
// we just start at (1 << 7) == 128.
|
||||||
FP_Base_DepTag = 128,
|
FP_Reg_Base = 128,
|
||||||
Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
|
Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
|
||||||
Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
|
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
|
||||||
};
|
};
|
||||||
|
|
||||||
// semantically meaningful register indices
|
// semantically meaningful register indices
|
||||||
|
|
|
@ -213,13 +213,13 @@ class CheckerCPU : public BaseCPU
|
||||||
|
|
||||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
||||||
{
|
{
|
||||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
|
||||||
return thread->readFloatReg(reg_idx);
|
return thread->readFloatReg(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
||||||
{
|
{
|
||||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
|
||||||
return thread->readFloatRegBits(reg_idx);
|
return thread->readFloatRegBits(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -239,7 +239,7 @@ class CheckerCPU : public BaseCPU
|
||||||
|
|
||||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
||||||
{
|
{
|
||||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
|
||||||
thread->setFloatReg(reg_idx, val);
|
thread->setFloatReg(reg_idx, val);
|
||||||
setResult<double>(val);
|
setResult<double>(val);
|
||||||
}
|
}
|
||||||
|
@ -247,7 +247,7 @@ class CheckerCPU : public BaseCPU
|
||||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||||
FloatRegBits val)
|
FloatRegBits val)
|
||||||
{
|
{
|
||||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
|
||||||
thread->setFloatRegBits(reg_idx, val);
|
thread->setFloatRegBits(reg_idx, val);
|
||||||
setResult<uint64_t>(val);
|
setResult<uint64_t>(val);
|
||||||
}
|
}
|
||||||
|
@ -294,14 +294,14 @@ class CheckerCPU : public BaseCPU
|
||||||
|
|
||||||
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
|
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
|
||||||
{
|
{
|
||||||
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
|
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
|
||||||
return thread->readMiscReg(reg_idx);
|
return thread->readMiscReg(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
void setMiscRegOperand(
|
void setMiscRegOperand(
|
||||||
const StaticInst *si, int idx, const MiscReg &val)
|
const StaticInst *si, int idx, const MiscReg &val)
|
||||||
{
|
{
|
||||||
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
|
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
|
||||||
return thread->setMiscReg(reg_idx, val);
|
return thread->setMiscReg(reg_idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -607,7 +607,7 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
|
||||||
thread->setFloatRegBits(idx, mismatch_val);
|
thread->setFloatRegBits(idx, mismatch_val);
|
||||||
break;
|
break;
|
||||||
case MiscRegClass:
|
case MiscRegClass:
|
||||||
thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
|
thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
|
||||||
mismatch_val);
|
mismatch_val);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -626,7 +626,7 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
|
||||||
break;
|
break;
|
||||||
case MiscRegClass:
|
case MiscRegClass:
|
||||||
// Try to get the proper misc register index for ARM here...
|
// Try to get the proper misc register index for ARM here...
|
||||||
thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
|
thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
|
||||||
break;
|
break;
|
||||||
// else Register is out of range...
|
// else Register is out of range...
|
||||||
}
|
}
|
||||||
|
|
|
@ -247,7 +247,7 @@ UseDefUnit::execute(int slot_idx)
|
||||||
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Float Reg %i"
|
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Float Reg %i"
|
||||||
" (%i) from Register File:%x (%08f).\n",
|
" (%i) from Register File:%x (%08f).\n",
|
||||||
tid, seq_num,
|
tid, seq_num,
|
||||||
reg_idx - FP_Base_DepTag, flat_idx,
|
reg_idx - FP_Reg_Base, flat_idx,
|
||||||
cpu->readFloatRegBits(flat_idx,
|
cpu->readFloatRegBits(flat_idx,
|
||||||
inst->readTid()),
|
inst->readTid()),
|
||||||
cpu->readFloatReg(flat_idx,
|
cpu->readFloatReg(flat_idx,
|
||||||
|
@ -269,7 +269,7 @@ UseDefUnit::execute(int slot_idx)
|
||||||
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Misc Reg %i "
|
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Misc Reg %i "
|
||||||
" (%i) from Register File:0x%x.\n",
|
" (%i) from Register File:0x%x.\n",
|
||||||
tid, seq_num,
|
tid, seq_num,
|
||||||
reg_idx - Ctrl_Base_DepTag, flat_idx,
|
reg_idx - Misc_Reg_Base, flat_idx,
|
||||||
cpu->readMiscReg(flat_idx,
|
cpu->readMiscReg(flat_idx,
|
||||||
inst->readTid()));
|
inst->readTid()));
|
||||||
inst->setIntSrc(ud_idx,
|
inst->setIntSrc(ud_idx,
|
||||||
|
@ -315,7 +315,7 @@ UseDefUnit::execute(int slot_idx)
|
||||||
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
|
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
|
||||||
" reg %i (%i) value 0x%x from "
|
" reg %i (%i) value 0x%x from "
|
||||||
"[sn:%i] to [sn:%i] source #%i.\n",
|
"[sn:%i] to [sn:%i] source #%i.\n",
|
||||||
tid, reg_idx - FP_Base_DepTag, flat_idx,
|
tid, reg_idx - FP_Reg_Base, flat_idx,
|
||||||
forward_inst->readFloatResult(dest_reg_idx),
|
forward_inst->readFloatResult(dest_reg_idx),
|
||||||
forward_inst->seqNum, inst->seqNum, ud_idx);
|
forward_inst->seqNum, inst->seqNum, ud_idx);
|
||||||
inst->setFloatSrc(ud_idx,
|
inst->setFloatSrc(ud_idx,
|
||||||
|
@ -329,7 +329,7 @@ UseDefUnit::execute(int slot_idx)
|
||||||
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
|
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
|
||||||
" reg %i (%i) value 0x%x from "
|
" reg %i (%i) value 0x%x from "
|
||||||
"[sn:%i] to [sn:%i] source #%i.\n",
|
"[sn:%i] to [sn:%i] source #%i.\n",
|
||||||
tid, reg_idx - Ctrl_Base_DepTag, flat_idx,
|
tid, reg_idx - Misc_Reg_Base, flat_idx,
|
||||||
forward_inst->readIntResult(dest_reg_idx),
|
forward_inst->readIntResult(dest_reg_idx),
|
||||||
forward_inst->seqNum,
|
forward_inst->seqNum,
|
||||||
inst->seqNum, ud_idx);
|
inst->seqNum, ud_idx);
|
||||||
|
@ -412,7 +412,7 @@ UseDefUnit::execute(int slot_idx)
|
||||||
tid, seq_num,
|
tid, seq_num,
|
||||||
inst->readFloatResult(ud_idx),
|
inst->readFloatResult(ud_idx),
|
||||||
inst->readFloatBitsResult(ud_idx),
|
inst->readFloatBitsResult(ud_idx),
|
||||||
reg_idx - FP_Base_DepTag, flat_idx);
|
reg_idx - FP_Reg_Base, flat_idx);
|
||||||
|
|
||||||
// Check for FloatRegBits Here
|
// Check for FloatRegBits Here
|
||||||
cpu->setFloatRegBits(flat_idx,
|
cpu->setFloatRegBits(flat_idx,
|
||||||
|
@ -425,7 +425,7 @@ UseDefUnit::execute(int slot_idx)
|
||||||
"idx %i (%i).\n",
|
"idx %i (%i).\n",
|
||||||
tid, seq_num, inst->readFloatResult(ud_idx),
|
tid, seq_num, inst->readFloatResult(ud_idx),
|
||||||
inst->readIntResult(ud_idx),
|
inst->readIntResult(ud_idx),
|
||||||
reg_idx - FP_Base_DepTag, flat_idx);
|
reg_idx - FP_Reg_Base, flat_idx);
|
||||||
|
|
||||||
cpu->setFloatReg(flat_idx,
|
cpu->setFloatReg(flat_idx,
|
||||||
inst->readFloatResult(ud_idx),
|
inst->readFloatResult(ud_idx),
|
||||||
|
@ -438,7 +438,7 @@ UseDefUnit::execute(int slot_idx)
|
||||||
tid, seq_num,
|
tid, seq_num,
|
||||||
inst->readFloatResult(ud_idx),
|
inst->readFloatResult(ud_idx),
|
||||||
inst->readIntResult(ud_idx),
|
inst->readIntResult(ud_idx),
|
||||||
reg_idx - FP_Base_DepTag, flat_idx);
|
reg_idx - FP_Reg_Base, flat_idx);
|
||||||
|
|
||||||
cpu->setFloatReg(flat_idx,
|
cpu->setFloatReg(flat_idx,
|
||||||
inst->readFloatResult(ud_idx),
|
inst->readFloatResult(ud_idx),
|
||||||
|
@ -458,7 +458,7 @@ UseDefUnit::execute(int slot_idx)
|
||||||
|
|
||||||
DPRINTF(InOrderUseDef, "[tid:%i]: Writing Misc. 0x%x "
|
DPRINTF(InOrderUseDef, "[tid:%i]: Writing Misc. 0x%x "
|
||||||
"to register idx %i.\n",
|
"to register idx %i.\n",
|
||||||
tid, inst->readIntResult(ud_idx), reg_idx - Ctrl_Base_DepTag);
|
tid, inst->readIntResult(ud_idx), reg_idx - Misc_Reg_Base);
|
||||||
|
|
||||||
// Remove Dependencies
|
// Remove Dependencies
|
||||||
regDepMap[tid]->removeFront(reg_type, flat_idx, inst);
|
regDepMap[tid]->removeFront(reg_type, flat_idx, inst);
|
||||||
|
|
|
@ -175,7 +175,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
|
||||||
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
|
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
|
||||||
{
|
{
|
||||||
return this->cpu->readMiscReg(
|
return this->cpu->readMiscReg(
|
||||||
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
|
si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
|
||||||
this->threadNumber);
|
this->threadNumber);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -185,7 +185,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
|
||||||
void setMiscRegOperand(const StaticInst *si, int idx,
|
void setMiscRegOperand(const StaticInst *si, int idx,
|
||||||
const MiscReg &val)
|
const MiscReg &val)
|
||||||
{
|
{
|
||||||
int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
|
int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
|
||||||
setMiscReg(misc_reg, val);
|
setMiscReg(misc_reg, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -953,7 +953,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case FloatRegClass:
|
case FloatRegClass:
|
||||||
src_reg = src_reg - TheISA::FP_Base_DepTag;
|
src_reg = src_reg - TheISA::FP_Reg_Base;
|
||||||
flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
|
flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
|
||||||
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
||||||
(int)src_reg, (int)flat_src_reg);
|
(int)src_reg, (int)flat_src_reg);
|
||||||
|
@ -961,7 +961,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case MiscRegClass:
|
case MiscRegClass:
|
||||||
flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
|
flat_src_reg = src_reg - TheISA::Misc_Reg_Base +
|
||||||
TheISA::NumFloatRegs + TheISA::NumIntRegs;
|
TheISA::NumFloatRegs + TheISA::NumIntRegs;
|
||||||
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
|
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
|
||||||
src_reg, flat_src_reg);
|
src_reg, flat_src_reg);
|
||||||
|
@ -1018,7 +1018,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case FloatRegClass:
|
case FloatRegClass:
|
||||||
dest_reg = dest_reg - TheISA::FP_Base_DepTag;
|
dest_reg = dest_reg - TheISA::FP_Reg_Base;
|
||||||
flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
|
flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
|
||||||
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
DPRINTF(Rename, "Flattening index %d to %d.\n",
|
||||||
(int)dest_reg, (int)flat_dest_reg);
|
(int)dest_reg, (int)flat_dest_reg);
|
||||||
|
@ -1028,7 +1028,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
|
||||||
case MiscRegClass:
|
case MiscRegClass:
|
||||||
// Floating point and Miscellaneous registers need their indexes
|
// Floating point and Miscellaneous registers need their indexes
|
||||||
// adjusted to account for the expanded number of flattened int regs.
|
// adjusted to account for the expanded number of flattened int regs.
|
||||||
flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
|
flat_dest_reg = dest_reg - TheISA::Misc_Reg_Base +
|
||||||
TheISA::NumIntRegs + TheISA::NumFloatRegs;
|
TheISA::NumIntRegs + TheISA::NumFloatRegs;
|
||||||
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
|
DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
|
||||||
dest_reg, flat_dest_reg);
|
dest_reg, flat_dest_reg);
|
||||||
|
|
|
@ -458,7 +458,7 @@ OzoneCPU<Impl>::tick()
|
||||||
|
|
||||||
_status = Running;
|
_status = Running;
|
||||||
thread.renameTable[ZeroReg]->setIntResult(0);
|
thread.renameTable[ZeroReg]->setIntResult(0);
|
||||||
thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
|
thread.renameTable[ZeroReg+TheISA::FP_Reg_Base]->
|
||||||
setDoubleResult(0.0);
|
setDoubleResult(0.0);
|
||||||
|
|
||||||
comm.advance();
|
comm.advance();
|
||||||
|
@ -727,7 +727,7 @@ OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
|
||||||
|
|
||||||
// Then loop through the floating point registers.
|
// Then loop through the floating point registers.
|
||||||
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
|
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
|
||||||
int fp_idx = i + TheISA::FP_Base_DepTag;
|
int fp_idx = i + TheISA::FP_Reg_Base;
|
||||||
thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
|
thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -756,7 +756,7 @@ template <class Impl>
|
||||||
double
|
double
|
||||||
OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
|
OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
|
||||||
{
|
{
|
||||||
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
int idx = reg_idx + TheISA::FP_Reg_Base;
|
||||||
return thread->renameTable[idx]->readFloatResult();
|
return thread->renameTable[idx]->readFloatResult();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -764,7 +764,7 @@ template <class Impl>
|
||||||
uint64_t
|
uint64_t
|
||||||
OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
|
OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
|
||||||
{
|
{
|
||||||
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
int idx = reg_idx + TheISA::FP_Reg_Base;
|
||||||
return thread->renameTable[idx]->readIntResult();
|
return thread->renameTable[idx]->readIntResult();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -783,7 +783,7 @@ template <class Impl>
|
||||||
void
|
void
|
||||||
OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
|
OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
|
||||||
{
|
{
|
||||||
int idx = reg_idx + TheISA::FP_Base_DepTag;
|
int idx = reg_idx + TheISA::FP_Reg_Base;
|
||||||
|
|
||||||
thread->renameTable[idx]->setDoubleResult(val);
|
thread->renameTable[idx]->setDoubleResult(val);
|
||||||
|
|
||||||
|
|
|
@ -65,19 +65,19 @@ inline
|
||||||
RegClass regIdxToClass(TheISA::RegIndex reg_idx,
|
RegClass regIdxToClass(TheISA::RegIndex reg_idx,
|
||||||
TheISA::RegIndex *rel_reg_idx = NULL)
|
TheISA::RegIndex *rel_reg_idx = NULL)
|
||||||
{
|
{
|
||||||
assert(reg_idx < TheISA::Max_DepTag);
|
assert(reg_idx < TheISA::Max_Reg_Index);
|
||||||
RegClass cl;
|
RegClass cl;
|
||||||
int offset;
|
int offset;
|
||||||
|
|
||||||
if (reg_idx < TheISA::FP_Base_DepTag) {
|
if (reg_idx < TheISA::FP_Reg_Base) {
|
||||||
cl = IntRegClass;
|
cl = IntRegClass;
|
||||||
offset = 0;
|
offset = 0;
|
||||||
} else if (reg_idx < TheISA::Ctrl_Base_DepTag) {
|
} else if (reg_idx < TheISA::Misc_Reg_Base) {
|
||||||
cl = FloatRegClass;
|
cl = FloatRegClass;
|
||||||
offset = TheISA::FP_Base_DepTag;
|
offset = TheISA::FP_Reg_Base;
|
||||||
} else {
|
} else {
|
||||||
cl = MiscRegClass;
|
cl = MiscRegClass;
|
||||||
offset = TheISA::Ctrl_Base_DepTag;
|
offset = TheISA::Misc_Reg_Base;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (rel_reg_idx)
|
if (rel_reg_idx)
|
||||||
|
|
|
@ -296,14 +296,14 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
||||||
{
|
{
|
||||||
numFpRegReads++;
|
numFpRegReads++;
|
||||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
|
||||||
return thread->readFloatReg(reg_idx);
|
return thread->readFloatReg(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
||||||
{
|
{
|
||||||
numFpRegReads++;
|
numFpRegReads++;
|
||||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
|
||||||
return thread->readFloatRegBits(reg_idx);
|
return thread->readFloatRegBits(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -316,7 +316,7 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
||||||
{
|
{
|
||||||
numFpRegWrites++;
|
numFpRegWrites++;
|
||||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
|
||||||
thread->setFloatReg(reg_idx, val);
|
thread->setFloatReg(reg_idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -324,7 +324,7 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
FloatRegBits val)
|
FloatRegBits val)
|
||||||
{
|
{
|
||||||
numFpRegWrites++;
|
numFpRegWrites++;
|
||||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
|
||||||
thread->setFloatRegBits(reg_idx, val);
|
thread->setFloatRegBits(reg_idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -362,7 +362,7 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
|
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
|
||||||
{
|
{
|
||||||
numIntRegReads++;
|
numIntRegReads++;
|
||||||
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
|
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
|
||||||
return thread->readMiscReg(reg_idx);
|
return thread->readMiscReg(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -370,7 +370,7 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
const StaticInst *si, int idx, const MiscReg &val)
|
const StaticInst *si, int idx, const MiscReg &val)
|
||||||
{
|
{
|
||||||
numIntRegWrites++;
|
numIntRegWrites++;
|
||||||
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
|
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
|
||||||
return thread->setMiscReg(reg_idx, val);
|
return thread->setMiscReg(reg_idx, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue