Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 7866241cf43416636cbd6a3a4f6eeda561ed2e27
This commit is contained in:
commit
2177d822ce
7 changed files with 142 additions and 101 deletions
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@ -75,6 +75,11 @@ class SyscallReturn {
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#endif
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#endif
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#if FULL_SYSTEM
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#include "arch/alpha/isa_fullsys_traits.hh"
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#endif
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namespace AlphaISA
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namespace AlphaISA
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{
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{
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@ -83,12 +88,6 @@ using namespace LittleEndianGuest;
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// redirected register map, really only used for the full system case.
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// redirected register map, really only used for the full system case.
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extern const int reg_redir[NumIntRegs];
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extern const int reg_redir[NumIntRegs];
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#if FULL_SYSTEM
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#include "arch/alpha/isa_fullsys_traits.hh"
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#endif
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StaticInstPtr decodeInst(ExtMachInst);
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StaticInstPtr decodeInst(ExtMachInst);
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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@ -5,7 +5,8 @@ class HelloWorld(AlphaLiveProcess):
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cmd = 'hello'
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cmd = 'hello'
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magicbus = Bus()
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magicbus = Bus()
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mem = PhysicalMemory(bus=magicbus)
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mem = PhysicalMemory()
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cpu = SimpleCPU(workload=HelloWorld(), mem=magicbus)
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cpu = SimpleCPU(workload=HelloWorld(), mem=magicbus)
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system = System(physmem=mem, cpu=cpu)
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system = System(physmem=mem, cpu=cpu)
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system.c1 = Connector(side_a=mem, side_b=magicbus)
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root = Root(system=system)
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root = Root(system=system)
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@ -34,7 +34,6 @@
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#include <cstdio>
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#include <cstdio>
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#include <string>
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#include <string>
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#include "arch/alpha/ev5.hh"
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#include "arch/alpha/system.hh"
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#include "arch/alpha/system.hh"
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#include "base/inifile.hh"
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/str.hh"
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@ -45,30 +44,17 @@
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#include "dev/simconsole.hh"
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#include "dev/simconsole.hh"
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#include "dev/simple_disk.hh"
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#include "dev/simple_disk.hh"
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#include "dev/tsunami_io.hh"
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#include "dev/tsunami_io.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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#include "sim/sim_object.hh"
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using namespace std;
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using namespace std;
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using namespace AlphaISA;
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using namespace AlphaISA;
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AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
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AlphaConsole::AlphaConsole(Params *p)
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AlphaSystem *s, BaseCPU *c, Platform *p,
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: PioDevice(p->name, p->platform), disk(p->disk),
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MemoryController *mmu, Addr a,
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console(params()->cons), system(params()->sys), cpu(params()->cpu),
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HierParams *hier, Bus *pio_bus)
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pioSize(sizeof(struct alphaAccess))
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: PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
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{
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (pio_bus) {
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pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
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&AlphaConsole::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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}
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alphaAccess = new Access;
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alphaAccess = new Access;
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alphaAccess->last_offset = size - 1;
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alphaAccess->last_offset = size - 1;
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@ -99,115 +85,117 @@ AlphaConsole::startup()
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alphaAccess->intrClockFrequency = platform->intrFrequency();
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alphaAccess->intrClockFrequency = platform->intrFrequency();
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}
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}
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Fault
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Tick
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AlphaConsole::read(MemReqPtr &req, uint8_t *data)
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AlphaConsole::read(Packet &pkt)
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{
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{
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memset(data, 0, req->size);
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pkt.time = curTick + pioDelay;
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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/** XXX Do we want to push the addr munging to a bus brige or something? So
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* the device has it's physical address and then the bridge adds on whatever
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* machine dependent address swizzle is required?
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*/
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switch (req->size)
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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Addr daddr = req.addr - pioAddr;
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switch (req.size)
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{
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{
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case sizeof(uint32_t):
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case sizeof(uint32_t):
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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if (!pkt.data) pkt.pkt.data = new uint32_t;
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*(uint32_t*)data);
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switch (daddr)
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switch (daddr)
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{
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{
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case offsetof(AlphaAccess, last_offset):
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case offsetof(AlphaAccess, last_offset):
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*(uint32_t*)data = alphaAccess->last_offset;
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*(uint32_t*)pkt.data = alphaAccess->last_offset;
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break;
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break;
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case offsetof(AlphaAccess, version):
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case offsetof(AlphaAccess, version):
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*(uint32_t*)data = alphaAccess->version;
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*(uint32_t*)pkt.data = alphaAccess->version;
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break;
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break;
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case offsetof(AlphaAccess, numCPUs):
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case offsetof(AlphaAccess, numCPUs):
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*(uint32_t*)data = alphaAccess->numCPUs;
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*(uint32_t*)pkt.data = alphaAccess->numCPUs;
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break;
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break;
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case offsetof(AlphaAccess, intrClockFrequency):
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case offsetof(AlphaAccess, intrClockFrequency):
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*(uint32_t*)data = alphaAccess->intrClockFrequency;
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*(uint32_t*)pkt.data = alphaAccess->intrClockFrequency;
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break;
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break;
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default:
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default:
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// Old console code read in everyting as a 32bit int
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/* Old console code read in everyting as a 32bit int
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*(uint32_t*)data = *(uint32_t*)(consoleData + daddr);
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* we now break that for better error checking.
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*/
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pkt.result = BadAddress;
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}
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}
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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*(uint32_t*)pkt.data);
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break;
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break;
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case sizeof(uint64_t):
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case sizeof(uint64_t):
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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if (!pkt.data) pkt.pkt.data = new uint64_t;
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*(uint64_t*)data);
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switch (daddr)
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switch (daddr)
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{
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{
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case offsetof(AlphaAccess, inputChar):
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case offsetof(AlphaAccess, inputChar):
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*(uint64_t*)data = console->console_in();
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*(uint64_t*)pkt.data = console->console_in();
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break;
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break;
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case offsetof(AlphaAccess, cpuClock):
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case offsetof(AlphaAccess, cpuClock):
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*(uint64_t*)data = alphaAccess->cpuClock;
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*(uint64_t*)pkt.data = alphaAccess->cpuClock;
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break;
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break;
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case offsetof(AlphaAccess, mem_size):
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case offsetof(AlphaAccess, mem_size):
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*(uint64_t*)data = alphaAccess->mem_size;
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*(uint64_t*)pkt.data = alphaAccess->mem_size;
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break;
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break;
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case offsetof(AlphaAccess, kernStart):
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case offsetof(AlphaAccess, kernStart):
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*(uint64_t*)data = alphaAccess->kernStart;
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*(uint64_t*)pkt.data = alphaAccess->kernStart;
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break;
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break;
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case offsetof(AlphaAccess, kernEnd):
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case offsetof(AlphaAccess, kernEnd):
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*(uint64_t*)data = alphaAccess->kernEnd;
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*(uint64_t*)pkt.data = alphaAccess->kernEnd;
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break;
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break;
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case offsetof(AlphaAccess, entryPoint):
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case offsetof(AlphaAccess, entryPoint):
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*(uint64_t*)data = alphaAccess->entryPoint;
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*(uint64_t*)pkt.data = alphaAccess->entryPoint;
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break;
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break;
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case offsetof(AlphaAccess, diskUnit):
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case offsetof(AlphaAccess, diskUnit):
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*(uint64_t*)data = alphaAccess->diskUnit;
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*(uint64_t*)pkt.data = alphaAccess->diskUnit;
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break;
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break;
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case offsetof(AlphaAccess, diskCount):
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case offsetof(AlphaAccess, diskCount):
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*(uint64_t*)data = alphaAccess->diskCount;
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*(uint64_t*)pkt.data = alphaAccess->diskCount;
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break;
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break;
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case offsetof(AlphaAccess, diskPAddr):
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case offsetof(AlphaAccess, diskPAddr):
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*(uint64_t*)data = alphaAccess->diskPAddr;
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*(uint64_t*)pkt.data = alphaAccess->diskPAddr;
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break;
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break;
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case offsetof(AlphaAccess, diskBlock):
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case offsetof(AlphaAccess, diskBlock):
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*(uint64_t*)data = alphaAccess->diskBlock;
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*(uint64_t*)pkt.data = alphaAccess->diskBlock;
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break;
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break;
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case offsetof(AlphaAccess, diskOperation):
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case offsetof(AlphaAccess, diskOperation):
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*(uint64_t*)data = alphaAccess->diskOperation;
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*(uint64_t*)pkt.data = alphaAccess->diskOperation;
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break;
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break;
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case offsetof(AlphaAccess, outputChar):
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case offsetof(AlphaAccess, outputChar):
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*(uint64_t*)data = alphaAccess->outputChar;
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*(uint64_t*)pkt.data = alphaAccess->outputChar;
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break;
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break;
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default:
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default:
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int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
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int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
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sizeof(alphaAccess->cpuStack[0]);
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sizeof(alphaAccess->cpuStack[0]);
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if (cpunum >= 0 && cpunum < 64)
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if (cpunum >= 0 && cpunum < 64)
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*(uint64_t*)data = alphaAccess->cpuStack[cpunum];
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*(uint64_t*)pkt.data = alphaAccess->cpuStack[cpunum];
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else
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else
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panic("Unknown 64bit access, %#x\n", daddr);
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panic("Unknown 64bit access, %#x\n", daddr);
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}
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}
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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*(uint64_t*)data);
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break;
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break;
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default:
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default:
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return genMachineCheckFault();
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pkt.result = BadAddress;
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}
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if (pkt.result == Unknown) pkt.result = Success;
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return pioDelay;
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}
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}
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return NoFault;
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Tick
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}
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Fault
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AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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{
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{
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uint64_t val;
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pkt.time = curTick + pioDelay;
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switch (req->size) {
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assert(pkt.result == Unknown);
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case sizeof(uint32_t):
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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val = *(uint32_t *)data;
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Addr daddr = req.addr - pioAddr;
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break;
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case sizeof(uint64_t):
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uint64_t val = *(uint64_t *)data;
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val = *(uint64_t *)data;
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assert(pkt.size == sizeof(uint64_t));
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break;
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default:
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return genMachineCheckFault();
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}
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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ExecContext *other_xc;
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switch (daddr) {
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switch (daddr) {
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case offsetof(AlphaAccess, diskUnit):
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case offsetof(AlphaAccess, diskUnit):
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@ -239,9 +227,6 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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console->out((char)(val & 0xff));
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console->out((char)(val & 0xff));
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break;
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break;
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other_xc->activate(); //Start the cpu
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break;
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default:
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default:
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int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
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int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
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sizeof(alphaAccess->cpuStack[0]);
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sizeof(alphaAccess->cpuStack[0]);
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@ -253,13 +238,9 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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panic("Unknown 64bit access, %#x\n", daddr);
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panic("Unknown 64bit access, %#x\n", daddr);
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}
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}
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return NoFault;
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pkt.result = Success;
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}
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Tick
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return pioDelay;
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AlphaConsole::cacheAccess(MemReqPtr &req)
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{
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return curTick + 1000;
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}
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}
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void
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void
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|
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@ -70,7 +70,7 @@ class MemoryController;
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* primarily used doing boot before the kernel has loaded its device
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* primarily used doing boot before the kernel has loaded its device
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* drivers.
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* drivers.
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*/
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*/
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class AlphaConsole : public PioDevice
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class AlphaConsole : public BasePioDevice
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{
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{
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protected:
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protected:
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struct Access : public AlphaAccess
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struct Access : public AlphaAccess
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@ -96,23 +96,29 @@ class AlphaConsole : public PioDevice
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/** a pointer to the CPU boot cpu */
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/** a pointer to the CPU boot cpu */
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BaseCPU *cpu;
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BaseCPU *cpu;
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Addr addr;
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public:
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static const Addr size = sizeof(struct AlphaAccess);
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struct Params : public BasePioDevice::Params
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|
{
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SimConsole *cons;
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SimpleDisk *disk;
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||||||
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AlphaSystem *sys;
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BaseCpu *cpu;
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||||||
|
};
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|
protected:
|
||||||
|
const Params *params() const {return (const Params *)_params; }
|
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|
|
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public:
|
public:
|
||||||
|
|
||||||
/** Standard Constructor */
|
/** Standard Constructor */
|
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AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
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AlphaConsole(Params *p);
|
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AlphaSystem *s, BaseCPU *c, Platform *platform,
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|
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MemoryController *mmu, Addr addr,
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|
||||||
HierParams *hier, Bus *pio_bus);
|
|
||||||
|
|
||||||
virtual void startup();
|
virtual void startup();
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* memory mapped reads and writes
|
* memory mapped reads and writes
|
||||||
*/
|
*/
|
||||||
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
virtual Tick read(Packet &pkt);
|
||||||
virtual Fault write(MemReqPtr &req, const uint8_t *data);
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virtual Tick write(Packet &pkt);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* standard serialization routines for checkpointing
|
* standard serialization routines for checkpointing
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -72,12 +72,6 @@ PioPort::SendEvent::process()
|
||||||
port->transmitList.push_back(&packet);
|
port->transmitList.push_back(&packet);
|
||||||
}
|
}
|
||||||
|
|
||||||
PioDevice::PioDevice(const std::string &name, Platform *p)
|
|
||||||
: SimObject(name), platform(p)
|
|
||||||
{
|
|
||||||
pioPort = new PioPort(this, p);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
bool
|
bool
|
||||||
PioPort::recvTiming(Packet &pkt)
|
PioPort::recvTiming(Packet &pkt)
|
||||||
|
@ -201,4 +195,13 @@ DmaDevice::~DmaDevice()
|
||||||
delete dmaPort;
|
delete dmaPort;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
BasePioDevice::addressRanges(AddrRangeList &range_list, bool &owner)
|
||||||
|
{
|
||||||
|
assert(pioSize != 0);
|
||||||
|
owner = true;
|
||||||
|
range_list.clear();
|
||||||
|
range_list.push_back(RangeSize(pio_addr, sizeof(struct alphaAccess)));
|
||||||
|
}
|
||||||
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|
||||||
|
|
||||||
|
|
|
@ -192,20 +192,40 @@ class PioDevice : public SimObject
|
||||||
|
|
||||||
/** Pure virtual function that the device must implement. Called when a read
|
/** Pure virtual function that the device must implement. Called when a read
|
||||||
* command is recieved by the port. */
|
* command is recieved by the port. */
|
||||||
virtual bool read(Packet &pkt) = 0;
|
virtual Tick read(Packet &pkt) = 0;
|
||||||
|
|
||||||
/** Pure virtual function that the device must implement. Called when a
|
/** Pure virtual function that the device must implement. Called when a
|
||||||
* write command is recieved by the port. */
|
* write command is recieved by the port. */
|
||||||
virtual bool write(Packet &pkt) = 0;
|
virtual Tick write(Packet &pkt) = 0;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
PioDevice(const std::string &name, Platform *p);
|
/** Params struct which is extended through each device based on the
|
||||||
|
* parameters it needs. Since we are re-writing everything, we might as well
|
||||||
|
* start from the bottom this time. */
|
||||||
|
|
||||||
|
struct Params
|
||||||
|
{
|
||||||
|
std::string name;
|
||||||
|
Platform *platform;
|
||||||
|
};
|
||||||
|
protected:
|
||||||
|
Params *_params;
|
||||||
|
|
||||||
|
public:
|
||||||
|
const Params *params() const { return _params; }
|
||||||
|
|
||||||
|
PioDevice(Params *params)
|
||||||
|
: SimObject(params()->name), platform(params()->platform)
|
||||||
|
{}
|
||||||
|
|
||||||
virtual ~PioDevice();
|
virtual ~PioDevice();
|
||||||
|
|
||||||
virtual Port *getPort(const std::string &if_name)
|
virtual Port *getPort(const std::string &if_name)
|
||||||
{
|
{
|
||||||
if (if_name == "pio")
|
if (if_name == "pio")
|
||||||
|
if (pioPort != NULL)
|
||||||
|
panic("pio port already connected to.");
|
||||||
|
pioPort = new PioPort(this, params()->platform);
|
||||||
return pioPort;
|
return pioPort;
|
||||||
else
|
else
|
||||||
return NULL;
|
return NULL;
|
||||||
|
@ -214,6 +234,33 @@ class PioDevice : public SimObject
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
class BasicPioDevice : public PioDevice
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
struct Params
|
||||||
|
{
|
||||||
|
Addr pio_addr;
|
||||||
|
Tick pio_delay;
|
||||||
|
};
|
||||||
|
|
||||||
|
protected:
|
||||||
|
/** Address that the device listens to. */
|
||||||
|
Addr pioAddr;
|
||||||
|
|
||||||
|
/** Size that the device's address range. */
|
||||||
|
Addr pioSize = 0;
|
||||||
|
|
||||||
|
/** Delay that the device experinces on an access. */
|
||||||
|
Tick pioDelay;
|
||||||
|
|
||||||
|
public:
|
||||||
|
BasePioDevice(Params *p)
|
||||||
|
: PioDevice(p), pioAddr(p->pio_addr), pioDelay(p->pioDelay)
|
||||||
|
{}
|
||||||
|
|
||||||
|
virtual void addressRanges(AddrRangeList &range_list, bool &owner);
|
||||||
|
};
|
||||||
|
|
||||||
class DmaDevice : public PioDevice
|
class DmaDevice : public PioDevice
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
|
|
|
@ -97,7 +97,11 @@ struct Packet
|
||||||
|
|
||||||
/** A pointer to the data being transfered. It can be differnt sizes
|
/** A pointer to the data being transfered. It can be differnt sizes
|
||||||
at each level of the heirarchy so it belongs in the packet,
|
at each level of the heirarchy so it belongs in the packet,
|
||||||
not request*/
|
not request.
|
||||||
|
This pointer may be NULL! If it isn't null when received by the producer
|
||||||
|
of data it refers to memory that has not been dynamically allocated.
|
||||||
|
Otherwise the producer should simply allocate dynamic memory to use.
|
||||||
|
*/
|
||||||
PacketDataPtr data;
|
PacketDataPtr data;
|
||||||
|
|
||||||
/** Indicates the size of the request. */
|
/** Indicates the size of the request. */
|
||||||
|
|
Loading…
Reference in a new issue