more steps toward O3 SMT
src/arch/mips/isa/formats/fp.isa: Adjust for newmem src/cpu/cpu_models.py: Use O3DynInst instead of convoluted way src/cpu/o3/alpha/impl.hh: take out O3DynInst typedef here ... src/cpu/o3/cpu.cc: open up the SMT functions in the O3CPU src/cpu/static_inst.hh: Add O3DynInst src/cpu/o3/dyn_inst.hh: Use to get ISA-specific O3DynInst --HG-- extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
This commit is contained in:
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f4c5609988
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215041215b
6 changed files with 82 additions and 56 deletions
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@ -142,10 +142,10 @@ output exec {{
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cpu->setFloatRegBits(inst, 0, mips_nan, size);
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cpu->setFloatRegBits(inst, 0, mips_nan, size);
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//Read FCSR from FloatRegFile
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//Read FCSR from FloatRegFile
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uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
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uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
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//Write FCSR from FloatRegFile
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//Write FCSR from FloatRegFile
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cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
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cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
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if (traceData) { traceData->setData(mips_nan); }
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if (traceData) { traceData->setData(mips_nan); }
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return true;
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return true;
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@ -158,12 +158,12 @@ output exec {{
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fpResetCauseBits(%(CPU_exec_context)s *cpu)
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fpResetCauseBits(%(CPU_exec_context)s *cpu)
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{
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{
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//Read FCSR from FloatRegFile
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//Read FCSR from FloatRegFile
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uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
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uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
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fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
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fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
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//Write FCSR from FloatRegFile
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//Write FCSR from FloatRegFile
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cpu->tc->setFloatRegBits(FCSR, fcsr);
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cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
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}
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}
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}};
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}};
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@ -176,8 +176,9 @@ def template FloatingPointExecute {{
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//When is the right time to reset cause bits?
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//When is the right time to reset cause bits?
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//start of every instruction or every cycle?
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//start of every instruction or every cycle?
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#if FULL_SYSTEM
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fpResetCauseBits(xc);
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fpResetCauseBits(xc);
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#endif
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%(op_decl)s;
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%(op_decl)s;
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%(op_rd)s;
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%(op_rd)s;
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@ -192,7 +193,10 @@ def template FloatingPointExecute {{
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//----
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//----
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//Check for IEEE 754 FP Exceptions
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//Check for IEEE 754 FP Exceptions
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//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
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//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
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if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
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if (
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#if FULL_SYSTEM
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!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
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#endif
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fault == NoFault)
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fault == NoFault)
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{
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{
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%(op_wb)s;
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%(op_wb)s;
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@ -79,18 +79,6 @@ CpuModel('OzoneCPU', 'ozone_exec.cc',
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CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
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CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
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'#include "cpu/checker/cpu.hh"',
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'#include "cpu/checker/cpu.hh"',
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{ 'CPU_exec_context': 'CheckerCPU' })
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{ 'CPU_exec_context': 'CheckerCPU' })
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# Maybe there is a more clever way to determine ISA
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# here but since the environment variable isnt passed through
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# here the easiest way is this...
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sub_template = 'not found'
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for argument in sys.argv:
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if 'ALPHA' in argument:
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sub_template = 'AlphaDynInst<AlphaSimpleImpl>'
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if sub_template == 'not found':
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sys.exit('NO CPU_exec_context substitution defined for this ISA')
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CpuModel('O3CPU', 'o3_cpu_exec.cc',
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CpuModel('O3CPU', 'o3_cpu_exec.cc',
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'#include "cpu/o3/isa_specific.hh"',
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'#include "cpu/o3/alpha/dyn_inst.hh"',
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{ 'CPU_exec_context': sub_template })
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{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
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@ -36,6 +36,7 @@
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#include "cpu/o3/alpha/params.hh"
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#include "cpu/o3/alpha/params.hh"
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#include "cpu/o3/cpu_policy.hh"
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#include "cpu/o3/cpu_policy.hh"
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// Forward declarations.
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// Forward declarations.
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template <class Impl>
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template <class Impl>
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class AlphaDynInst;
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class AlphaDynInst;
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@ -88,7 +89,4 @@ struct AlphaSimpleImpl
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/** The O3Impl to be used. */
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/** The O3Impl to be used. */
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typedef AlphaSimpleImpl O3CPUImpl;
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typedef AlphaSimpleImpl O3CPUImpl;
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/** The O3Impl to be used. */
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typedef DynInst O3DynInst;
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#endif // __CPU_O3_ALPHA_IMPL_HH__
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#endif // __CPU_O3_ALPHA_IMPL_HH__
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@ -463,14 +463,13 @@ template <class Impl>
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void
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void
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FullO3CPU<Impl>::insertThread(unsigned tid)
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FullO3CPU<Impl>::insertThread(unsigned tid)
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{
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{
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DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
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DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
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// Will change now that the PC and thread state is internal to the CPU
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// Will change now that the PC and thread state is internal to the CPU
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// and not in the ThreadContext.
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// and not in the ThreadContext.
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#if 0
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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ThreadContext *src_tc = system->threadContexts[tid];
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ThreadContext *src_tc = system->threadContexts[tid];
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#else
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#else
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ThreadContext *src_tc = thread[tid];
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ThreadContext *src_tc = tcBase(tid);
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#endif
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#endif
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//Bind Int Regs to Rename Map
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//Bind Int Regs to Rename Map
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@ -490,11 +489,14 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
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}
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}
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//Copy Thread Data Into RegFile
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//Copy Thread Data Into RegFile
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this->copyFromTC(tid);
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//this->copyFromTC(tid);
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//Set PC/NPC
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//Set PC/NPC/NNPC
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regFile.pc[tid] = src_tc->readPC();
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setPC(src_tc->readPC(), tid);
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regFile.npc[tid] = src_tc->readNextPC();
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setNextPC(src_tc->readNextPC(), tid);
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#if THE_ISA != ALPHA_ISA
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setNextNPC(src_tc->readNextNPC(), tid);
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#endif
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src_tc->setStatus(ThreadContext::Active);
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src_tc->setStatus(ThreadContext::Active);
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@ -503,16 +505,19 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
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//Reset ROB/IQ/LSQ Entries
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//Reset ROB/IQ/LSQ Entries
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commit.rob->resetEntries();
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commit.rob->resetEntries();
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iew.resetEntries();
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iew.resetEntries();
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#endif
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}
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}
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template <class Impl>
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template <class Impl>
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void
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void
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FullO3CPU<Impl>::removeThread(unsigned tid)
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FullO3CPU<Impl>::removeThread(unsigned tid)
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{
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{
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DPRINTF(O3CPU,"[tid:%i] Removing thread data");
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DPRINTF(O3CPU,"[tid:%i] Removing thread from CPU.");
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#if 0
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//Unbind Int Regs from Rename Map
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// Copy Thread Data From RegFile
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// If thread is suspended, it might be re-allocated
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//this->copyToTC(tid);
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// Unbind Int Regs from Rename Map
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for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
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for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
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PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
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PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
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@ -520,7 +525,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
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freeList.addReg(phys_reg);
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freeList.addReg(phys_reg);
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}
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}
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//Unbind Float Regs from Rename Map
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// Unbind Float Regs from Rename Map
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for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
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for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
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PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
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PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
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freeList.addReg(phys_reg);
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freeList.addReg(phys_reg);
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}
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}
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//Copy Thread Data From RegFile
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// Squash Throughout Pipeline
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/* Fix Me:
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* Do we really need to do this if we are removing a thread
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* in the sense that it's finished (exiting)? If the thread is just
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* being suspended we might...
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*/
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// this->copyToTC(tid);
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//Squash Throughout Pipeline
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fetch.squash(0,tid);
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fetch.squash(0,tid);
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decode.squash(tid);
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decode.squash(tid);
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rename.squash(tid);
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rename.squash(tid);
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assert(iew.ldstQueue.getCount(tid) == 0);
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assert(iew.ldstQueue.getCount(tid) == 0);
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//Reset ROB/IQ/LSQ Entries
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// Reset ROB/IQ/LSQ Entries
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if (activeThreads.size() >= 1) {
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if (activeThreads.size() >= 1) {
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commit.rob->resetEntries();
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commit.rob->resetEntries();
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iew.resetEntries();
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iew.resetEntries();
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}
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}
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#endif
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}
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}
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void
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void
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FullO3CPU<Impl>::suspendContext(int tid)
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FullO3CPU<Impl>::suspendContext(int tid)
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{
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{
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DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
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DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
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unscheduleTickEvent();
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unscheduleTickEvent();
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_status = Idle;
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_status = Idle;
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/*
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/*
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void
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void
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FullO3CPU<Impl>::deallocateContext(int tid)
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FullO3CPU<Impl>::deallocateContext(int tid)
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{
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{
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DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
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DPRINTF(O3CPU,"[tid:%i]: Deallocating Thread Context", tid);
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/*
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//Remove From Active List, if Active
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list<unsigned>::iterator isActive = find(
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activeThreads.begin(), activeThreads.end(), tid);
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if (isActive != activeThreads.end()) {
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//Remove From Active List, if Active
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list<unsigned>::iterator thread_it =
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find(activeThreads.begin(), activeThreads.end(), tid);
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if (thread_it != activeThreads.end()) {
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DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
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DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
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tid);
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tid);
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activeThreads.erase(isActive);
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activeThreads.erase(thread_it);
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removeThread(tid);
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removeThread(tid);
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}
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}
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*/
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}
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}
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template <class Impl>
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template <class Impl>
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void
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void
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FullO3CPU<Impl>::haltContext(int tid)
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FullO3CPU<Impl>::haltContext(int tid)
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{
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{
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DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
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DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid);
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/*
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/*
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//Remove From Active List, if Active
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//Remove From Active List, if Active
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list<unsigned>::iterator isActive = find(
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list<unsigned>::iterator isActive = find(
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39
src/cpu/o3/dyn_inst.hh
Normal file
39
src/cpu/o3/dyn_inst.hh
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_DYN_INST_HH__
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#define __CPU_O3_DYN_INST_HH__
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#include "cpu/o3/isa_specific.hh"
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/** The O3Impl to be used. */
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typedef DynInst O3DynInst;
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#endif // __CPU_O3_DYN_INST_HH__
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@ -53,6 +53,8 @@ class Packet;
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template <class Impl>
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template <class Impl>
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class AlphaDynInst;
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class AlphaDynInst;
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//class O3DynInst;
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template <class Impl>
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template <class Impl>
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class OzoneDynInst;
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class OzoneDynInst;
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Loading…
Reference in a new issue