eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
--HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
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01c959aeaf
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202d7f62b9
10 changed files with 5 additions and 36 deletions
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@ -94,8 +94,6 @@ AlphaISA::processInterrupts(CPU *cpu)
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int ipl = 0;
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int ipl = 0;
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int summary = 0;
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int summary = 0;
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cpu->checkInterrupts = false;
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if (cpu->readMiscReg(IPR_ASTRR))
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if (cpu->readMiscReg(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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panic("asynchronous traps not implemented\n");
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@ -155,8 +153,6 @@ SimpleThread::hwrei()
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if (!misspeculating()) {
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if (!misspeculating()) {
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if (kernelStats)
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if (kernelStats)
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kernelStats->hwrei();
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kernelStats->hwrei();
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cpu->checkInterrupts = true;
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}
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}
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// FIXME: XXX check for interrupts? XXX
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// FIXME: XXX check for interrupts? XXX
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@ -50,7 +50,6 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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case MISCREG_SOFTINT_CLR:
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case MISCREG_SOFTINT_CLR:
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return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
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return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
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case MISCREG_SOFTINT_SET:
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case MISCREG_SOFTINT_SET:
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->post_interrupt(soft_interrupt);
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tc->getCpuPtr()->post_interrupt(soft_interrupt);
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return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
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return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
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@ -80,15 +79,9 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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break;
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break;
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case MISCREG_PSTATE:
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case MISCREG_PSTATE:
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if (val & PSTATE::ie && !(pstate & PSTATE::ie)) {
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tc->getCpuPtr()->checkInterrupts = true;
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}
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setReg(miscReg, val);
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setReg(miscReg, val);
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case MISCREG_PIL:
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case MISCREG_PIL:
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if (val < pil) {
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tc->getCpuPtr()->checkInterrupts = true;
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}
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setReg(miscReg, val);
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setReg(miscReg, val);
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break;
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break;
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@ -112,7 +105,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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setReg(miscReg, val);
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setReg(miscReg, val);
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tc->getCpuPtr()->checkInterrupts = true;
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//do something to post mondo interrupt
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break;
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break;
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case MISCREG_HSTICK_CMPR:
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case MISCREG_HSTICK_CMPR:
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@ -208,7 +201,6 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
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(stick_cmpr & mask(63)));
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(stick_cmpr & mask(63)));
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if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
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if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
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tc->getCpuPtr()->post_interrupt(soft_interrupt);
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tc->getCpuPtr()->post_interrupt(soft_interrupt);
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tc->getCpuPtr()->checkInterrupts = true;
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setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
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setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
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}
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}
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} else
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} else
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@ -232,7 +224,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
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if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
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if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
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setRegWithEffect(MISCREG_HINTP, 1, tc);
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setRegWithEffect(MISCREG_HINTP, 1, tc);
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tc->getCpuPtr()->post_interrupt(hstick_match);
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tc->getCpuPtr()->post_interrupt(hstick_match);
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tc->getCpuPtr()->checkInterrupts = true;
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}
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}
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// Need to do something to cause interrupt to happen here !!! @todo
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// Need to do something to cause interrupt to happen here !!! @todo
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} else
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} else
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@ -96,7 +96,7 @@ CPUProgressEvent::description()
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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BaseCPU::BaseCPU(Params *p)
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BaseCPU::BaseCPU(Params *p)
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: MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true),
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: MemObject(p->name), clock(p->clock), instCnt(0),
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params(p), number_of_threads(p->numberOfThreads), system(p->system),
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params(p), number_of_threads(p->numberOfThreads), system(p->system),
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phase(p->phase)
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phase(p->phase)
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#else
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#else
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@ -334,7 +334,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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interrupts = oldCPU->interrupts;
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interrupts = oldCPU->interrupts;
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checkInterrupts = oldCPU->checkInterrupts;
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for (int i = 0; i < threadContexts.size(); ++i)
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for (int i = 0; i < threadContexts.size(); ++i)
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threadContexts[i]->profileClear();
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threadContexts[i]->profileClear();
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@ -371,7 +370,6 @@ BaseCPU::post_interrupt(int int_type)
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void
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void
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BaseCPU::post_interrupt(int int_num, int index)
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BaseCPU::post_interrupt(int int_num, int index)
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{
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{
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checkInterrupts = true;
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interrupts.post(int_num, index);
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interrupts.post(int_num, index);
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}
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}
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@ -106,7 +106,6 @@ class BaseCPU : public MemObject
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virtual void post_interrupt(int int_num, int index);
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virtual void post_interrupt(int int_num, int index);
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virtual void clear_interrupt(int int_num, int index);
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virtual void clear_interrupt(int int_num, int index);
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virtual void clear_interrupts();
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virtual void clear_interrupts();
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bool checkInterrupts;
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bool check_interrupts(ThreadContext * tc) const
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bool check_interrupts(ThreadContext * tc) const
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{ return interrupts.check_interrupts(tc); }
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{ return interrupts.check_interrupts(tc); }
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@ -217,8 +217,6 @@ AlphaO3CPU<Impl>::hwrei(unsigned tid)
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this->thread[tid]->kernelStats->hwrei();
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this->thread[tid]->kernelStats->hwrei();
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this->checkInterrupts = true;
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// FIXME: XXX check for interrupts? XXX
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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return NoFault;
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}
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}
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@ -270,7 +268,6 @@ AlphaO3CPU<Impl>::processInterrupts(Fault interrupt)
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this->interrupts.updateIntrInfo(this->threadContexts[0]);
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this->interrupts.updateIntrInfo(this->threadContexts[0]);
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DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
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DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
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this->checkInterrupts = false;
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this->trap(interrupt, 0);
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this->trap(interrupt, 0);
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}
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}
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@ -671,8 +671,7 @@ DefaultCommit<Impl>::commit()
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} else {
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} else {
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DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
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DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
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}
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}
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} else if (cpu->checkInterrupts &&
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} else if (cpu->check_interrupts(cpu->tcBase(0)) &&
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cpu->check_interrupts(cpu->tcBase(0)) &&
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commitStatus[0] != TrapPending &&
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commitStatus[0] != TrapPending &&
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!trapSquash[0] &&
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!trapSquash[0] &&
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!tcSquash[0]) {
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!tcSquash[0]) {
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@ -245,7 +245,6 @@ SparcO3CPU<Impl>::processInterrupts(Fault interrupt)
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this->interrupts.updateIntrInfo(this->threadContexts[0]);
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this->interrupts.updateIntrInfo(this->threadContexts[0]);
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DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
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DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
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this->checkInterrupts = false;
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this->trap(interrupt, 0);
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this->trap(interrupt, 0);
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}
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}
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@ -182,10 +182,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
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globalSeqNum = 1;
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globalSeqNum = 1;
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#if FULL_SYSTEM
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checkInterrupts = false;
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#endif
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lockFlag = 0;
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lockFlag = 0;
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// Setup rename table, initializing all values to ready.
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// Setup rename table, initializing all values to ready.
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@ -684,8 +680,6 @@ OzoneCPU<Impl>::hwrei()
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lockAddrList.clear();
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lockAddrList.clear();
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thread.kernelStats->hwrei();
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thread.kernelStats->hwrei();
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checkInterrupts = true;
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// FIXME: XXX check for interrupts? XXX
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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return NoFault;
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}
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}
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@ -704,7 +698,6 @@ OzoneCPU<Impl>::processInterrupts()
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if (interrupt != NoFault) {
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if (interrupt != NoFault) {
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this->interrupts.updateIntrInfo(thread.getTC());
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this->interrupts.updateIntrInfo(thread.getTC());
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this->checkInterrupts = false;
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interrupt->invoke(thread.getTC());
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interrupt->invoke(thread.getTC());
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}
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}
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}
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}
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@ -88,7 +88,6 @@ InorderBackEnd<Impl>::checkInterrupts()
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int ipl = 0;
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int ipl = 0;
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int summary = 0;
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int summary = 0;
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cpu->checkInterrupts = false;
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if (thread->readMiscReg(IPR_ASTRR))
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if (thread->readMiscReg(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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panic("asynchronous traps not implemented\n");
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@ -151,8 +150,7 @@ InorderBackEnd<Impl>::tick()
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// I'm waiting for it to drain. (for now just squash)
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// I'm waiting for it to drain. (for now just squash)
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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if (interruptBlocked ||
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if (interruptBlocked ||
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(cpu->checkInterrupts &&
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cpu->check_interrupts(tc)) {
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cpu->check_interrupts(tc))) {
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if (!robEmpty()) {
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if (!robEmpty()) {
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interruptBlocked = true;
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interruptBlocked = true;
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//AlphaDep
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//AlphaDep
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@ -311,12 +311,11 @@ void
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BaseSimpleCPU::checkForInterrupts()
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BaseSimpleCPU::checkForInterrupts()
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{
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{
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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if (checkInterrupts && check_interrupts(tc)) {
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if (check_interrupts(tc)) {
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Fault interrupt = interrupts.getInterrupt(tc);
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Fault interrupt = interrupts.getInterrupt(tc);
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if (interrupt != NoFault) {
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if (interrupt != NoFault) {
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interrupts.updateIntrInfo(tc);
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interrupts.updateIntrInfo(tc);
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checkInterrupts = false;
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interrupt->invoke(tc);
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interrupt->invoke(tc);
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}
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}
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}
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}
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