cpu: Support exit when any one Trace CPU completes replay

This change adds a Trace CPU param to exit simulation early,
i.e. when the first (any one) trace execution is complete. With
this change the user gets a choice to configure exit as either
when the last CPU finishes (default) or first CPU finishes
replay. Configuring an early exit enables simulating and
measuring stats strictly when memory-system resources are being
stressed by all Trace CPUs.

Change-Id: I3998045fdcc5cd343e1ca92d18dd7f7ecdba8f1d
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Radhika Jagtap 2016-09-15 18:01:20 +01:00
parent d067327fc0
commit 1fe5f63137
3 changed files with 32 additions and 6 deletions

View file

@ -75,3 +75,8 @@ class TraceCPU(BaseCPU):
# frequency as was used for generating the traces.
freqMultiplier = Param.Float(1.0, "Multiplier scale the Trace CPU "\
"frequency up or down")
# Enable exiting when any one Trace CPU completes execution which is set to
# false by default
enableEarlyExit = Param.Bool(False, "Exit when any one Trace CPU "\
"completes execution")

View file

@ -61,7 +61,8 @@ TraceCPU::TraceCPU(TraceCPUParams *params)
dcacheNextEvent(this),
oneTraceComplete(false),
traceOffset(0),
execCompleteEvent(nullptr)
execCompleteEvent(nullptr),
enableEarlyExit(params->enableEarlyExit)
{
// Increment static counter for number of Trace CPUs.
++TraceCPU::numTraceCPUs;
@ -137,12 +138,18 @@ TraceCPU::init()
// events using a relative tick delta
dcacheGen.adjustInitTraceOffset(traceOffset);
// The static counter for number of Trace CPUs is correctly set at this
// point so create an event and pass it.
// If the Trace CPU simulation is configured to exit on any one trace
// completion then we don't need a counted event to count down all Trace
// CPUs in the system. If not then instantiate a counted event.
if (!enableEarlyExit) {
// The static counter for number of Trace CPUs is correctly set at
// this point so create an event and pass it.
execCompleteEvent = new CountedExitEvent("end of all traces reached.",
numTraceCPUs);
}
}
void
TraceCPU::schedIcacheNext()
{
@ -191,9 +198,17 @@ TraceCPU::checkAndSchedExitEvent()
// Schedule event to indicate execution is complete as both
// instruction and data access traces have been played back.
inform("%s: Execution complete.\n", name());
// If the replay is configured to exit early, that is when any one
// execution is complete then exit immediately and return. Otherwise,
// schedule the counted exit that counts down completion of each Trace
// CPU.
if (enableEarlyExit) {
exitSimLoop("End of trace reached");
} else {
schedule(*execCompleteEvent, curTick());
}
}
}
void
TraceCPU::regStats()

View file

@ -1116,6 +1116,12 @@ class TraceCPU : public BaseCPU
*/
CountedExitEvent *execCompleteEvent;
/**
* Exit when any one Trace CPU completes its execution. If this is
* configured true then the execCompleteEvent is not scheduled.
*/
const bool enableEarlyExit;
Stats::Scalar numSchedDcacheEvent;
Stats::Scalar numSchedIcacheEvent;