ARM: Make sure macroops aren't interrupted midinstruction.

Do this by setting the delayed commit flag for all but the last microop.

src/arch/arm/insts/macromem.cc

@@ -128,6 +128,13 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
     }
 
     (*uop)->setLastMicroop();
+
+    for (StaticInstPtr *curUop = microOps;
+            !(*curUop)->isLastMicroop(); curUop++) {
+        MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
+        assert(uopPtr);
+        uopPtr->setDelayedCommit();
+    }
 }
 
 MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
@@ -198,6 +205,13 @@ MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
 
     assert(numMicroops == i);
     microOps[numMicroops - 1]->setLastMicroop();
+
+    for (StaticInstPtr *curUop = microOps;
+            !(*curUop)->isLastMicroop(); curUop++) {
+        MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
+        assert(uopPtr);
+        uopPtr->setDelayedCommit();
+    }
 }
 
 }

src/arch/arm/insts/macromem.hh

@@ -60,10 +60,26 @@ number_of_ones(int32_t val)
     return ones;
 }
 
+class MicroOp : public PredOp
+{
+  protected:
+    MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
+            : PredOp(mnem, machInst, __opClass)
+    {
+    }
+
+  public:
+    void
+    setDelayedCommit()
+    {
+        flags[IsDelayedCommit] = true;
+    }
+};
+
 /**
  * Microops of the form IntRegA = IntRegB op Imm
  */
-class MicroIntOp : public PredOp
+class MicroIntOp : public MicroOp
 {
   protected:
     RegIndex ura, urb;
@@ -71,7 +87,7 @@ class MicroIntOp : public PredOp
 
     MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
                RegIndex _ura, RegIndex _urb, uint8_t _imm)
-            : PredOp(mnem, machInst, __opClass),
+            : MicroOp(mnem, machInst, __opClass),
               ura(_ura), urb(_urb), imm(_imm)
     {
     }