Big changes to use the new microcode assembler.
--HG-- extra : convert_revision : 7d1a43c5791a2e7e30533746da3dd7036a5b8799
This commit is contained in:
Gabe Black
parent
ce8f4c1f16
commit
1f7ed5b7b4
7 changed files with 179 additions and 131 deletions
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@ -60,27 +60,13 @@
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// Instructions that do the same thing to multiple sets of arguments.
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//
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let {{
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def doInst(name, Name, opTypeSet):
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if not instDict.has_key(Name):
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raise Exception, "Unrecognized instruction: %s" % Name
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inst = instDict[Name]()
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return inst.emit(opTypeSet)
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}};
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def format Inst(*opTypeSet) {{
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(header_output,
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decoder_output,
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decode_block,
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exce_output) = doInst(name, Name, list(opTypeSet)).makeList()
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decode_block = specializeInst(Name, list(opTypeSet), EmulEnv())
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}};
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def format MultiInst(switchVal, *opTypeSets) {{
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switcher = {}
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for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets):
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switcher[count] = (opTypeSet,)
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(header_output,
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decoder_output,
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decode_block,
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exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher).makeList()
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switcher[count] = (opTypeSet, EmulEnv())
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decode_block = doSplitDecode(Name, specializeInst, switchVal, switcher)
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}};
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@ -99,6 +99,7 @@ output header {{
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#include "arch/x86/faults.hh"
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#include "arch/x86/isa_traits.hh"
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#include "arch/x86/regfile.hh"
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#include "arch/x86/types.hh"
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#include "base/misc.hh"
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#include "cpu/static_inst.hh"
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#include "mem/packet.hh"
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@ -106,6 +107,9 @@ output header {{
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}};
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output decoder {{
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namespace X86Macroop {
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};
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#include "base/cprintf.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/thread_context.hh" // for Jump::branchTarget()
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@ -71,7 +71,7 @@ def template MacroExecPanic {{
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output header {{
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// Base class for macroops
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// Base class for combinationally generated macroops
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class MacroOp : public StaticInst
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{
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protected:
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@ -113,14 +113,17 @@ output header {{
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// Basic instruction class declaration template.
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def template MacroDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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namespace X86Microop
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{
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public:
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// Constructor.
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%(class_name)s(ExtMachInst machInst);
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor.
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%(class_name)s(ExtMachInst machInst);
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};
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};
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}};
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@ -142,24 +145,82 @@ def template MacroConstructor {{
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//
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let {{
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def genMacroOp(name, Name, opSeq):
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numMicroOps = len(opSeq)
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allocMicroOps = ''
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micropc = 0
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for op in opSeq:
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allocMicroOps += \
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"microOps[%d] = %s;\n" % \
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(micropc, op.getAllocator('"' + name + '"', True, False,
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#op.delayed,
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micropc == 0,
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micropc == numMicroOps - 1))
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micropc += 1
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iop = InstObjParams(name, Name, 'MacroOp',
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{'code' : '', 'num_micro_ops' : numMicroOps,
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'alloc_micro_ops' : allocMicroOps})
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header_output = MacroDeclare.subst(iop)
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decoder_output = MacroConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = ''
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return (header_output, decoder_output, decode_block, exec_output)
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from micro_asm import Combinational_Macroop, Rom_Macroop
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class X86Macroop(Combinational_Macroop):
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def __init__(self, name):
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super(X86Macroop, self).__init__(name)
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self.directives = {
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}
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self.declared = False
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def getAllocator(self, env):
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return "new X86Macroop::%s(machInst)" % self.name
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def getDeclaration(self):
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#FIXME This first parameter should be the mnemonic. I need to
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#write some code which pulls that out
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iop = InstObjParams(self.name, self.name, "Macroop", {"code" : ""})
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return MacroDeclare.subst(iop);
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def getDefinition(self):
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#FIXME This first parameter should be the mnemonic. I need to
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#write some code which pulls that out
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numMicroops = len(self.microops)
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allocMicroops = ''
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micropc = 0
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for op in self.microops:
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allocMicroops += \
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"microOps[%d] = %s;\n" % \
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(micropc, op.getAllocator(True, False,
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micropc == 0,
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micropc == numMicroops - 1))
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micropc += 1
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iop = InstObjParams(self.name, self.name, "Macroop",
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{"code" : "", "num_micro_ops" : numMicroops,
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"alloc_micro_ops" : allocMicroops})
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return MacroConstructor.subst(iop);
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}};
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output header {{
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struct EmulEnv
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{
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X86ISA::RegIndex reg;
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X86ISA::RegIndex regm;
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uint64_t immediate;
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uint64_t displacement;
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int addressSize;
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int dataSize;
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EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm,
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uint64_t _immediate, uint64_t _displacement,
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int _addressSize, int _dataSize) :
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reg(_reg), regm(_regm),
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immediate(_immediate), displacement(_displacement),
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addressSize(_addressSize), dataSize(_dataSize)
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{;}
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};
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}};
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let {{
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class EmulEnv(object):
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def __init__(self):
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self.reg = "Not specified"
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self.regm = "Not specified"
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self.immediate = "IMMEDIATE"
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self.displacement = "DISPLACEMENT"
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self.addressSize = "ADDRSIZE"
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self.dataSize = "OPSIZE"
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def getAllocator(self):
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return "EmulEmv(%(reg)s, %(regm)s, %(immediate)s, %(displacement)s, %(addressSize)s, %(dataSize)s)" % \
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self.__dict__()
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}};
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let {{
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def genMacroop(Name, env):
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if not macroopDict.has_key(Name):
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raise Exception, "Unrecognized instruction: %s" % Name
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macroop = macroopDict[Name]
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if not macroop.declared:
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global header_output
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global decoder_output
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header_output = macroop.getDeclaration()
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decoder_output = macroop.getDefinition()
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return "return %s;\n" % macroop.getAllocator(env)
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}};
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@ -72,34 +72,9 @@
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namespace X86ISA;
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////////////////////////////////////////////////////////////////////
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//
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// General infrastructure code. These files provide infrastructure
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// which was developed to support x86 but isn't specific to it.
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//
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//Include code to build macroops.
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##include "macroop.isa"
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////////////////////////////////////////////////////////////////////
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//
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// X86 only infrastructure code.
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//
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//Include the base class for x86 instructions, and some support code.
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##include "base.isa"
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//Include code to specialize an instruction template to operate on
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//a particular set of operands. This is specific to x86 and the x86
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//microcode ISA.
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##include "specialize.isa"
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////////////////////////////////////////////////////////////////////
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//
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// Code which directly specifies isa components like instructions
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// microops, and the decoder.
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//
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//Include the definitions for the instruction formats
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##include "formats/formats.isa"
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@ -112,8 +87,17 @@ namespace X86ISA;
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//internal instruction set.
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##include "microops/microops.isa"
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//Include the instruction definitions which are microop assembler programs.
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##include "insts/insts.isa"
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//Include code to build macroops.
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##include "macroop.isa"
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//Include the simple microcode assembler. This will hopefully stay
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//unspecialized for x86 and can later be made available to other ISAs.
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##include "microasm.isa"
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//Include code to specialize an instruction template to operate on
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//a particular set of operands. This is specific to x86 and the x86
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//microcode ISA.
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##include "specialize.isa"
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//Include the bitfield definitions
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##include "bitfields.isa"
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@ -55,6 +55,20 @@
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//
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// Authors: Gabe Black
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//##include "microops/microops.isa"
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//##include "macroop.isa"
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let {{
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import sys
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sys.path[0:0] = ["src/arch/x86/isa/"]
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from insts import microcode
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print microcode
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from micro_asm import MicroAssembler, Rom_Macroop, Rom
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mainRom = Rom('main ROM')
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assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
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macroopDict = assembler.assemble(microcode)
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Microcode assembler specialization for x86
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@ -88,6 +102,5 @@ let {{
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return text
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def getAllocator(self, mnemonic, *microFlags):
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args = ''
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return 'new %s(machInst, %s%s%s)' % (self.className, mnemonic, self.microFlagsText(microFlags), args)
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return 'new %s(machInst, %s)' % (self.className, mnemonic, self.microFlagsText(microFlags))
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}};
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@ -221,7 +221,7 @@ def template MicroRegOpImmConstructor {{
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}};
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let {{
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class RegOp(object):
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class RegOp(X86Microop):
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def __init__(self, dest, src1, src2):
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self.dest = dest
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self.src1 = src1
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@ -243,7 +243,7 @@ let {{
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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class RegOpImm(object):
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class RegOpImm(X86Microop):
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def __init__(self, dest, src1, imm):
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self.dest = dest
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self.src1 = src1
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@ -274,10 +274,11 @@ let {{
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decoder_output = ""
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exec_output = ""
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def defineMicroIntOp(mnemonic, code):
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def defineMicroRegOp(mnemonic, code):
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global header_output
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global decoder_output
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global exec_output
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global microopClasses
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Name = mnemonic
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name = mnemonic.lower()
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@ -296,7 +297,8 @@ let {{
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class RegOpChild(RegOp):
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def __init__(self, dest, src1, src2):
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super(RegOpChild, self).__init__(self, dest, src1, src2)
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super(RegOpChild, self).__init__(dest, src1, src2)
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self.className = Name
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self.mnemonic = name
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microopClasses[name] = RegOpChild
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@ -310,19 +312,20 @@ let {{
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class RegOpImmChild(RegOpImm):
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def __init__(self, dest, src1, imm):
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super(RegOpImmChild, self).__init__(self, dest, src1, imm)
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super(RegOpImmChild, self).__init__(dest, src1, imm)
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self.className = Name + "Imm"
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self.mnemonic = name + "i"
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microopClasses[name + "i"] = RegOpChild
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defineMicroIntOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
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defineMicroIntOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
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defineMicroIntOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
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defineMicroIntOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
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defineMicroIntOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
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defineMicroIntOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
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defineMicroIntOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
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defineMicroIntOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
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defineMicroIntOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
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defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
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defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
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defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
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defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
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defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
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defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
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defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
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}};
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@ -66,24 +66,23 @@ let {{
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# vals is a dict which matches case values with what should be decoded to.
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# builder is called on the exploded contents of "vals" values to generate
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# whatever code should be used.
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def doSplitDecode(name, Name, builder, switchVal, vals, default = None):
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blocks = OutputBlocks()
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blocks.decode_block += 'switch(%s) {\n' % switchVal
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def doSplitDecode(Name, builder, switchVal, vals, default = None):
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decode_block = 'switch(%s) {\n' % switchVal
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for (val, todo) in vals.items():
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built = builder(name, Name, *todo)
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built.decode_block = '\tcase %s: %s\n' % (val, built.decode_block)
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blocks.append(built)
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new_block = builder(Name, *todo)
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new_block = '\tcase %s: %s\n' % (val, new_block)
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decode_block += new_block
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if default:
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built = builder(name, Name, *default)
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built.decode_block = '\tdefault: %s\n' % built.decode_block
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blocks.append(built)
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blocks.decode_block += '}\n'
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return blocks
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new_block = builder(Name, *default)
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new_block = '\tdefault: %s\n' % new_block
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decode_block += new_block
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decode_block += '}\n'
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return decode_block
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}};
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let {{
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class OpType(object):
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parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Za-z0-9][A-Za-z0-9]*))")
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parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Z0-9])(?P<rsize>[a-z]*))")
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def __init__(self, opTypeString):
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match = OpType.parser.search(opTypeString)
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if match == None:
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@ -91,74 +90,72 @@ let {{
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self.reg = match.group("reg")
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self.tag = match.group("tag")
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self.size = match.group("size")
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self.rsize = match.group("rsize")
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# This function specializes the given piece of code to use a particular
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# set of argument types described by "opTypes". These are "implemented"
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# in reverse order.
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def specializeInst(name, Name, code, opTypes):
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opNum = len(opTypes) - 1
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# set of argument types described by "opTypes".
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def specializeInst(Name, opTypes, env):
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while len(opTypes):
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# print "Building a composite op with tags", opTypes
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# print "And code", code
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opNum = len(opTypes) - 1
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# A regular expression to find the operand placeholders we're
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# interested in.
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opRe = re.compile("\\^(?P<operandNum>%d)(?=[^0-9]|$)" % opNum)
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# Parse the operand type strign we're working with
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# Parse the operand type string we're working with
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opType = OpType(opTypes[opNum])
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if opType.reg:
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#Figure out what to do with fixed register operands
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if opType.reg in ("Ax", "Bx", "Cx", "Dx"):
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code = opRe.sub("%%{INTREG_R%s}" % opType.reg.upper(), code)
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elif opType.reg == "Al":
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# We need a way to specify register width
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code = opRe.sub("%{INTREG_RAX}", code)
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else:
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print "Didn't know how to encode fixed register %s!" % opType.reg
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#This is the index to use, so we should stick it some place.
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print "INTREG_R%s" % (opType.reg + opType.size.upper())
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if opType.size:
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if opType.rsize in ("l", "h", "b"):
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print "byte"
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elif opType.rsize == "x":
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print "word"
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else:
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print "Didn't recognize fixed register size %s!" % opType.rsize
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elif opType.tag == None or opType.size == None:
|
||||
raise Exception, "Problem parsing operand tag: %s" % opType.tag
|
||||
elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"):
|
||||
# Use the "reg" field of the ModRM byte to select the register
|
||||
code = opRe.sub("%{(uint8_t)MODRM_REG}", code)
|
||||
print "(uint8_t)MODRM_REG"
|
||||
elif opType.tag in ("E", "Q", "W"):
|
||||
# This might refer to memory or to a register. We need to
|
||||
# divide it up farther.
|
||||
regCode = opRe.sub("%{(uint8_t)MODRM_RM}", code)
|
||||
print "(uint8_t)MODRM_RM"
|
||||
regTypes = copy.copy(opTypes)
|
||||
regTypes.pop(-1)
|
||||
regTypes.pop(0)
|
||||
regEnv = copy.copy(env)
|
||||
# This needs to refer to memory, but we'll fill in the details
|
||||
# later. It needs to take into account unaligned memory
|
||||
# addresses.
|
||||
code = "GenFault ${new UnimpInstFault}\n" + code
|
||||
memCode = opRe.sub("%0", code)
|
||||
# code = "GenFault #${new UnimpInstFault}#\n" + code
|
||||
print "%0"
|
||||
memTypes = copy.copy(opTypes)
|
||||
memTypes.pop(-1)
|
||||
return doSplitDecode(name, Name, specializeInst, "MODRM_MOD",
|
||||
{"3" : (regCode, regTypes)}, (memCode, memTypes))
|
||||
memTypes.pop(0)
|
||||
memEnv = copy.copy(env)
|
||||
return doSplitDecode(Name, specializeInst, "MODRM_MOD",
|
||||
{"3" : (regTypes, memEnv)}, (memTypes, memEnv))
|
||||
elif opType.tag in ("I", "J"):
|
||||
# Immediates are already in the instruction, so don't leave in
|
||||
# those parameters
|
||||
code = opRe.sub("${IMMEDIATE}", code)
|
||||
print "IMMEDIATE"
|
||||
elif opType.tag == "M":
|
||||
# This needs to refer to memory, but we'll fill in the details
|
||||
# later. It needs to take into account unaligned memory
|
||||
# addresses.
|
||||
code = "GenFault ${new UnimpInstFault}\n" + code
|
||||
code = opRe.sub("%0", code)
|
||||
#code = "GenFault #${new UnimpInstFault}#\n" + code
|
||||
print "%0"
|
||||
elif opType.tag in ("PR", "R", "VR"):
|
||||
# There should probably be a check here to verify that mod
|
||||
# is equal to 11b
|
||||
code = opRe.sub("%{(uint8_t)MODRM_RM}", code)
|
||||
print "(uint8_t)MODRM_RM"
|
||||
else:
|
||||
raise Exception, "Unrecognized tag %s." % opType.tag
|
||||
opTypes.pop(-1)
|
||||
opTypes.pop(0)
|
||||
|
||||
# At this point, we've built up "code" to have all the necessary extra
|
||||
# instructions needed to implement whatever types of operands were
|
||||
# specified. Now we'll assemble it it into a StaticInst.
|
||||
blocks = OutputBlocks()
|
||||
blocks.append(assembleMicro(name, Name, code))
|
||||
return blocks
|
||||
return genMacroop(Name, env)
|
||||
}};
|
||||
|
|
|
|||
Loading…
Reference in a new issue