ARM: Implement CLREX
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66bcbec96e
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1f032ad345
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@ -194,7 +194,7 @@ def format Thumb32BranchesAndMiscCtrl() {{
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case 0x1:
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case 0x1:
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return new Enterx(machInst);
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return new Enterx(machInst);
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case 0x2:
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case 0x2:
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return new WarnUnimplemented("clrex", machInst);
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return new Clrex(machInst);
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case 0x4:
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case 0x4:
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return new WarnUnimplemented("dsb", machInst);
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return new WarnUnimplemented("dsb", machInst);
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case 0x5:
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case 0x5:
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@ -97,7 +97,7 @@ def format ArmUnconditional() {{
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} else if (op1 == 0x57) {
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} else if (op1 == 0x57) {
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switch (op2) {
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switch (op2) {
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case 0x1:
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case 0x1:
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return new WarnUnimplemented("clrex", machInst);
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return new Clrex(machInst);
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case 0x4:
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case 0x4:
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return new WarnUnimplemented("dsb", machInst);
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return new WarnUnimplemented("dsb", machInst);
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case 0x5:
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case 0x5:
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@ -668,6 +668,17 @@ let {{
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decoder_output += ImmOpConstructor.subst(setendIop)
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decoder_output += ImmOpConstructor.subst(setendIop)
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exec_output += PredOpExecute.subst(setendIop)
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exec_output += PredOpExecute.subst(setendIop)
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clrexCode = '''
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unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
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fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
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'''
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clrexIop = InstObjParams("clrex", "Clrex","PredOp",
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{ "code": clrexCode,
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"predicate_test": predicateTest },[])
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header_output += BasicDeclare.subst(clrexIop)
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decoder_output += BasicConstructor.subst(clrexIop)
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exec_output += PredOpExecute.subst(clrexIop)
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cpsCode = '''
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cpsCode = '''
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uint32_t mode = bits(imm, 4, 0);
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uint32_t mode = bits(imm, 4, 0);
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uint32_t f = bits(imm, 5);
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uint32_t f = bits(imm, 5);
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@ -355,6 +355,13 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
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DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
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DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
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& UserMode);
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& UserMode);
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// If this is a clrex instruction, provide a PA of 0 with no fault
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// This will force the monitor to set the tracked address to 0
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// a bit of a hack but this effectively clrears this processors monitor
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if (flags & Clrex){
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req->setPaddr(0);
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return NoFault;
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}
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if (!is_fetch) {
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if (!is_fetch) {
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assert(flags & MustBeOne);
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assert(flags & MustBeOne);
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if (sctlr.a || !(flags & AllowUnaligned)) {
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if (sctlr.a || !(flags & AllowUnaligned)) {
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@ -78,7 +78,8 @@ class TLB : public BaseTLB
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// Because zero otherwise looks like a valid setting and may be used
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// Because zero otherwise looks like a valid setting and may be used
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// accidentally, this bit must be non-zero to show it was used on
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// accidentally, this bit must be non-zero to show it was used on
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// purpose.
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// purpose.
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MustBeOne = 0x20
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MustBeOne = 0x20,
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Clrex = 0x40
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};
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};
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protected:
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protected:
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typedef std::multimap<Addr, int> PageTable;
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typedef std::multimap<Addr, int> PageTable;
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