stats: updates due to changes to x86, stale configs.
This commit is contained in:
Nilay Vaish
parent
8e07b36d2b
commit
1efe42fa97
173 changed files with 11984 additions and 8983 deletions
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@ -648,10 +648,11 @@ sequential_access=false
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size=4194304
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[system.cpu.toL2Bus]
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type=CoherentBus
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type=CoherentXBar
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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header_cycles=1
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snoop_filter=Null
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system=system
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use_default_range=false
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width=32
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@ -730,7 +731,7 @@ eventq_index=0
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sys=system
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[system.iobus]
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type=NoncoherentBus
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type=NoncoherentXBar
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clk_domain=system.clk_domain
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eventq_index=0
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header_cycles=1
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@ -776,11 +777,12 @@ sequential_access=false
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size=1024
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[system.membus]
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type=CoherentBus
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type=CoherentXBar
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children=badaddr_responder
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clk_domain=system.clk_domain
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eventq_index=0
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header_cycles=1
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snoop_filter=Null
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system=system
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use_default_range=false
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width=8
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@ -808,8 +810,33 @@ pio=system.membus.default
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[system.physmem]
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type=DRAMCtrl
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IDD0=0.075000
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IDD02=0.000000
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IDD2N=0.050000
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IDD2N2=0.000000
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IDD2P0=0.000000
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IDD2P02=0.000000
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IDD2P1=0.000000
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IDD2P12=0.000000
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IDD3N=0.057000
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IDD3N2=0.000000
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IDD3P0=0.000000
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IDD3P02=0.000000
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IDD3P1=0.000000
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IDD3P12=0.000000
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IDD4R=0.187000
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IDD4R2=0.000000
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IDD4W=0.165000
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IDD4W2=0.000000
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IDD5=0.220000
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IDD52=0.000000
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IDD6=0.000000
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IDD62=0.000000
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VDD=1.500000
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VDD2=0.000000
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activation_limit=4
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addr_mapping=RoRaBaChCo
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bank_groups_per_rank=0
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banks_per_rank=8
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burst_length=8
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channels=1
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@ -818,6 +845,7 @@ conf_table_reported=true
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device_bus_width=8
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device_rowbuffer_size=1024
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devices_per_rank=8
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dll=true
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
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@ -831,19 +859,26 @@ read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCCD_L=0
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tCK=1250
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tCL=13750
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tCS=2500
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tRAS=35000
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tRCD=13750
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tREFI=7800000
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tRFC=260000
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tRP=13750
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tRRD=6000
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tRRD_L=0
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tRTP=7500
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tRTW=2500
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tWR=15000
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tWTR=7500
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tXAW=30000
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tXP=0
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tXPDLL=0
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tXS=0
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tXSDLL=0
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write_buffer_size=64
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write_high_thresh_perc=85
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write_low_thresh_perc=50
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@ -932,6 +967,7 @@ HeaderType=0
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InterruptLine=30
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InterruptPin=1
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LatencyTimer=0
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LegacyIOBase=0
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MSICAPBaseOffset=0
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MSICAPCapId=0
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MSICAPMaskBits=0
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@ -1387,6 +1423,7 @@ HeaderType=0
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InterruptLine=31
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InterruptPin=1
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LatencyTimer=0
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LegacyIOBase=0
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MSICAPBaseOffset=0
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MSICAPCapId=0
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MSICAPMaskBits=0
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@ -90,6 +90,7 @@ do_statistics_insts=true
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dtb=system.cpu0.dtb
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eventq_index=0
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fetchBufferSize=64
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fetchQueueSize=32
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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@ -142,7 +143,6 @@ switched_out=false
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system=system
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tracer=system.cpu0.tracer
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=
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dcache_port=system.cpu0.dcache.cpu_side
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@ -596,6 +596,7 @@ do_statistics_insts=true
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dtb=system.cpu1.dtb
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eventq_index=0
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fetchBufferSize=64
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fetchQueueSize=32
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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@ -648,7 +649,6 @@ switched_out=false
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system=system
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tracer=system.cpu1.tracer
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=
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dcache_port=system.cpu1.dcache.cpu_side
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@ -1139,7 +1139,7 @@ eventq_index=0
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sys=system
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[system.iobus]
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type=NoncoherentBus
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type=NoncoherentXBar
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clk_domain=system.clk_domain
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eventq_index=0
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header_cycles=1
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@ -1220,11 +1220,12 @@ sequential_access=false
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size=4194304
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[system.membus]
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type=CoherentBus
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type=CoherentXBar
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children=badaddr_responder
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clk_domain=system.clk_domain
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eventq_index=0
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header_cycles=1
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snoop_filter=Null
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system=system
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use_default_range=false
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width=8
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@ -1252,8 +1253,33 @@ pio=system.membus.default
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[system.physmem]
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type=DRAMCtrl
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IDD0=0.075000
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IDD02=0.000000
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IDD2N=0.050000
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IDD2N2=0.000000
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IDD2P0=0.000000
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IDD2P02=0.000000
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IDD2P1=0.000000
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IDD2P12=0.000000
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IDD3N=0.057000
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IDD3N2=0.000000
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IDD3P0=0.000000
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IDD3P02=0.000000
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IDD3P1=0.000000
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IDD3P12=0.000000
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IDD4R=0.187000
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IDD4R2=0.000000
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IDD4W=0.165000
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IDD4W2=0.000000
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IDD5=0.220000
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IDD52=0.000000
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IDD6=0.000000
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IDD62=0.000000
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VDD=1.500000
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VDD2=0.000000
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activation_limit=4
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addr_mapping=RoRaBaChCo
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bank_groups_per_rank=0
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banks_per_rank=8
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burst_length=8
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channels=1
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@ -1262,6 +1288,7 @@ conf_table_reported=true
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device_bus_width=8
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device_rowbuffer_size=1024
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devices_per_rank=8
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dll=true
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
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@ -1275,19 +1302,26 @@ read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCCD_L=0
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tCK=1250
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tCL=13750
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tCS=2500
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tRAS=35000
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tRCD=13750
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tREFI=7800000
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tRFC=260000
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tRP=13750
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tRRD=6000
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tRRD_L=0
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tRTP=7500
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tRTW=2500
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tWR=15000
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tWTR=7500
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tXAW=30000
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tXP=0
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tXPDLL=0
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tXS=0
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tXSDLL=0
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write_buffer_size=64
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write_high_thresh_perc=85
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write_low_thresh_perc=50
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@ -1315,10 +1349,11 @@ output=true
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port=3456
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[system.toL2Bus]
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type=CoherentBus
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type=CoherentXBar
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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header_cycles=1
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snoop_filter=Null
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system=system
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use_default_range=false
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width=8
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@ -1387,6 +1422,7 @@ HeaderType=0
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InterruptLine=30
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InterruptPin=1
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LatencyTimer=0
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LegacyIOBase=0
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MSICAPBaseOffset=0
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MSICAPCapId=0
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MSICAPMaskBits=0
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@ -1842,6 +1878,7 @@ HeaderType=0
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InterruptLine=31
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InterruptPin=1
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LatencyTimer=0
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LegacyIOBase=0
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MSICAPBaseOffset=0
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MSICAPCapId=0
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MSICAPMaskBits=0
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@ -90,6 +90,7 @@ do_statistics_insts=true
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dtb=system.cpu.dtb
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eventq_index=0
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fetchBufferSize=64
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fetchQueueSize=32
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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@ -142,7 +143,6 @@ switched_out=false
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system=system
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tracer=system.cpu.tracer
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=
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dcache_port=system.cpu.dcache.cpu_side
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@ -597,10 +597,11 @@ sequential_access=false
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size=4194304
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[system.cpu.toL2Bus]
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type=CoherentBus
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type=CoherentXBar
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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header_cycles=1
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snoop_filter=Null
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system=system
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use_default_range=false
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width=32
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@ -679,7 +680,7 @@ eventq_index=0
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sys=system
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[system.iobus]
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type=NoncoherentBus
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type=NoncoherentXBar
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clk_domain=system.clk_domain
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eventq_index=0
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header_cycles=1
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@ -725,11 +726,12 @@ sequential_access=false
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size=1024
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[system.membus]
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type=CoherentBus
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type=CoherentXBar
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children=badaddr_responder
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clk_domain=system.clk_domain
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eventq_index=0
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header_cycles=1
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snoop_filter=Null
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system=system
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use_default_range=false
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width=8
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@ -757,8 +759,33 @@ pio=system.membus.default
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[system.physmem]
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type=DRAMCtrl
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IDD0=0.075000
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IDD02=0.000000
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IDD2N=0.050000
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IDD2N2=0.000000
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IDD2P0=0.000000
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IDD2P02=0.000000
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IDD2P1=0.000000
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IDD2P12=0.000000
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IDD3N=0.057000
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IDD3N2=0.000000
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IDD3P0=0.000000
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IDD3P02=0.000000
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IDD3P1=0.000000
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IDD3P12=0.000000
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IDD4R=0.187000
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IDD4R2=0.000000
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IDD4W=0.165000
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IDD4W2=0.000000
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IDD5=0.220000
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IDD52=0.000000
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IDD6=0.000000
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IDD62=0.000000
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VDD=1.500000
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VDD2=0.000000
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activation_limit=4
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addr_mapping=RoRaBaChCo
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bank_groups_per_rank=0
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banks_per_rank=8
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burst_length=8
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channels=1
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@ -767,6 +794,7 @@ conf_table_reported=true
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device_bus_width=8
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device_rowbuffer_size=1024
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devices_per_rank=8
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dll=true
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
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@ -780,19 +808,26 @@ read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCCD_L=0
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tCK=1250
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tCL=13750
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tCS=2500
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tRAS=35000
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tRCD=13750
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tREFI=7800000
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tRFC=260000
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tRP=13750
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tRRD=6000
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tRRD_L=0
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tRTP=7500
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tRTW=2500
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tWR=15000
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tWTR=7500
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tXAW=30000
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tXP=0
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tXPDLL=0
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tXS=0
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tXSDLL=0
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write_buffer_size=64
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write_high_thresh_perc=85
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write_low_thresh_perc=50
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@ -881,6 +916,7 @@ HeaderType=0
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InterruptLine=30
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InterruptPin=1
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LatencyTimer=0
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LegacyIOBase=0
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MSICAPBaseOffset=0
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MSICAPCapId=0
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MSICAPMaskBits=0
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@ -1336,6 +1372,7 @@ HeaderType=0
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InterruptLine=31
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InterruptPin=1
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LatencyTimer=0
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LegacyIOBase=0
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MSICAPBaseOffset=0
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MSICAPCapId=0
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MSICAPMaskBits=0
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@ -84,9 +84,6 @@ max_loads_any_thread=0
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numThreads=1
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profile=0
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progress_interval=0
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simpoint_interval=100000000
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simpoint_profile=false
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simpoint_profile_file=simpoint.bb.gz
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simpoint_start_insts=
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simulate_data_stalls=false
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simulate_inst_stalls=false
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@ -273,6 +270,7 @@ do_statistics_insts=true
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dtb=system.cpu2.dtb
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eventq_index=0
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fetchBufferSize=64
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fetchQueueSize=32
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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@ -325,7 +323,6 @@ switched_out=true
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system=system
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tracer=system.cpu2.tracer
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=
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@ -740,7 +737,7 @@ eventq_index=0
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sys=system
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[system.iobus]
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type=NoncoherentBus
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type=NoncoherentXBar
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clk_domain=system.clk_domain
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eventq_index=0
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header_cycles=1
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@ -821,11 +818,12 @@ sequential_access=false
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size=4194304
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[system.membus]
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type=CoherentBus
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type=CoherentXBar
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children=badaddr_responder
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clk_domain=system.clk_domain
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eventq_index=0
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header_cycles=1
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snoop_filter=Null
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system=system
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use_default_range=false
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width=8
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@ -853,8 +851,33 @@ pio=system.membus.default
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[system.physmem]
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type=DRAMCtrl
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IDD0=0.075000
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IDD02=0.000000
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IDD2N=0.050000
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IDD2N2=0.000000
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IDD2P0=0.000000
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IDD2P02=0.000000
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IDD2P1=0.000000
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IDD2P12=0.000000
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IDD3N=0.057000
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IDD3N2=0.000000
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IDD3P0=0.000000
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IDD3P02=0.000000
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IDD3P1=0.000000
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IDD3P12=0.000000
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IDD4R=0.187000
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IDD4R2=0.000000
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IDD4W=0.165000
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IDD4W2=0.000000
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IDD5=0.220000
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IDD52=0.000000
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IDD6=0.000000
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IDD62=0.000000
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VDD=1.500000
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VDD2=0.000000
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activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -863,6 +886,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -876,19 +900,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -916,10 +947,11 @@ output=true
|
|||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -988,6 +1020,7 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1443,6 +1476,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.cpu0]
|
||||
type=MinorCPU
|
||||
children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer
|
||||
children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
|
||||
branchPred=system.cpu0.branchPred
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
|
@ -184,14 +184,14 @@ predType=tournament
|
|||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -199,15 +199,15 @@ sequential_access=false
|
|||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
mem_side=system.cpu0.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
|
@ -237,7 +237,7 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[5]
|
||||
port=system.cpu0.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -254,7 +254,7 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
port=system.cpu0.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.executeFuncUnits]
|
||||
type=MinorFUPool
|
||||
|
|
@ -643,34 +643,34 @@ opClass=InstPrefetch
|
|||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
mem_side=system.cpu0.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -729,7 +729,7 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[4]
|
||||
port=system.cpu0.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -746,7 +746,71 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
port=system.cpu0.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.l2cache]
|
||||
type=BaseCache
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu0.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu0.l2cache.tags
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.toL2Bus.master[0]
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu0.l2cache.tags]
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
|
||||
[system.cpu0.toL2Bus]
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu0.l2cache.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -754,7 +818,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu1]
|
||||
type=MinorCPU
|
||||
children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer
|
||||
children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
|
||||
branchPred=system.cpu1.branchPred
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
|
@ -839,14 +903,14 @@ predType=tournament
|
|||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -854,15 +918,15 @@ sequential_access=false
|
|||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
mem_side=system.cpu1.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu1.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
|
@ -892,7 +956,7 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[11]
|
||||
port=system.cpu1.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -909,7 +973,7 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[9]
|
||||
port=system.cpu1.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu1.executeFuncUnits]
|
||||
type=MinorFUPool
|
||||
|
|
@ -1298,34 +1362,34 @@ opClass=InstPrefetch
|
|||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
mem_side=system.cpu1.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu1.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -1384,7 +1448,7 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[10]
|
||||
port=system.cpu1.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -1401,7 +1465,71 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[8]
|
||||
port=system.cpu1.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu1.l2cache]
|
||||
type=BaseCache
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu1.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu1.l2cache.tags
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.toL2Bus.master[0]
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu1.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu1.l2cache.tags]
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
|
||||
[system.cpu1.toL2Bus]
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu1.l2cache.cpu_side
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -1429,13 +1557,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -1460,7 +1588,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -1509,11 +1637,12 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -1541,8 +1670,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1551,6 +1705,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -1564,19 +1719,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -1584,12 +1746,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -1644,6 +1806,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1728,6 +1891,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -2046,15 +2219,16 @@ output=true
|
|||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
|
|
|
|||
|
|
@ -784,10 +784,11 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -820,13 +821,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -851,7 +852,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -865,11 +866,12 @@ sequential_access=false
|
|||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -897,8 +899,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -907,6 +934,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -920,19 +948,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -940,12 +975,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -1000,6 +1035,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1084,6 +1120,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ load_offset=0
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -101,10 +101,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -119,19 +119,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -151,20 +152,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -182,7 +183,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -190,8 +190,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -203,7 +203,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.checker]
|
||||
type=O3Checker
|
||||
|
|
@ -433,14 +433,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -453,10 +453,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -468,275 +468,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -883,10 +841,11 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -919,13 +878,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -950,7 +909,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -964,11 +923,12 @@ sequential_access=false
|
|||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -996,8 +956,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1006,6 +991,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -1019,19 +1005,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -1039,12 +1032,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -1099,6 +1092,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1183,6 +1177,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -101,10 +101,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -119,19 +119,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -151,20 +152,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -182,7 +183,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -190,8 +190,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -203,7 +203,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -283,14 +283,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -303,10 +303,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -318,275 +318,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -733,10 +691,11 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -769,13 +728,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -800,7 +759,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -814,11 +773,12 @@ sequential_access=false
|
|||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -846,8 +806,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -856,6 +841,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -869,19 +855,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -889,12 +882,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -949,6 +942,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1033,6 +1027,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ load_offset=0
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.realview.nvmem system.physmem
|
||||
memories=system.physmem system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -124,9 +124,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -504,6 +501,7 @@ dstage2_mmu=system.cpu2.dstage2_mmu
|
|||
dtb=system.cpu2.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -527,7 +525,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysCCRegs=1280
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
|
|
@ -557,7 +555,6 @@ switched_out=true
|
|||
system=system
|
||||
tracer=system.cpu2.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=
|
||||
|
||||
|
|
@ -1018,13 +1015,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -1049,7 +1046,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -1098,11 +1095,12 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -1130,8 +1128,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1140,6 +1163,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -1153,19 +1177,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -1173,12 +1204,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -1233,6 +1264,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1317,6 +1349,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -1635,10 +1677,11 @@ output=true
|
|||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -129,6 +129,7 @@ dstage2_mmu=system.cpu0.dstage2_mmu
|
|||
dtb=system.cpu0.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -152,7 +153,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysCCRegs=1280
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
|
|
@ -182,7 +183,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=
|
||||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
|
|
@ -733,6 +733,7 @@ dstage2_mmu=system.cpu1.dstage2_mmu
|
|||
dtb=system.cpu1.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -756,7 +757,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysCCRegs=1280
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
|
|
@ -786,7 +787,6 @@ switched_out=true
|
|||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=
|
||||
|
||||
|
|
@ -1247,13 +1247,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -1278,7 +1278,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -1327,11 +1327,12 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -1359,8 +1360,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1369,6 +1395,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -1382,19 +1409,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -1402,12 +1436,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -1462,6 +1496,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1546,6 +1581,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -1864,10 +1909,11 @@ output=true
|
|||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ load_offset=0
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -487,13 +487,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -518,7 +518,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -567,11 +567,12 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -599,8 +600,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -609,6 +635,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -622,19 +649,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -642,12 +676,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -702,6 +736,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -786,6 +821,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -1104,10 +1149,11 @@ output=true
|
|||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ type=Bridge
|
|||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
master=system.iobus.slave[0]
|
||||
|
|
@ -120,6 +120,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -172,7 +173,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -730,10 +730,11 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -762,8 +763,8 @@ transition_latency=100000000
|
|||
|
||||
[system.e820_table]
|
||||
type=X86E820Table
|
||||
children=entries0 entries1 entries2 entries3
|
||||
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
|
||||
children=entries0 entries1 entries2 entries3 entries4
|
||||
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
|
||||
eventq_index=0
|
||||
|
||||
[system.e820_table.entries0]
|
||||
|
|
@ -789,6 +790,13 @@ size=133169152
|
|||
|
||||
[system.e820_table.entries3]
|
||||
type=X86E820Entry
|
||||
addr=134217728
|
||||
eventq_index=0
|
||||
range_type=2
|
||||
size=3087007744
|
||||
|
||||
[system.e820_table.entries4]
|
||||
type=X86E820Entry
|
||||
addr=4294901760
|
||||
eventq_index=0
|
||||
range_type=2
|
||||
|
|
@ -837,13 +845,13 @@ version=17
|
|||
[system.intel_mp_table.base_entries02]
|
||||
type=X86IntelMPBus
|
||||
bus_id=0
|
||||
bus_type=ISA
|
||||
bus_type=PCI
|
||||
eventq_index=0
|
||||
|
||||
[system.intel_mp_table.base_entries03]
|
||||
type=X86IntelMPBus
|
||||
bus_id=1
|
||||
bus_type=PCI
|
||||
bus_type=ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.intel_mp_table.base_entries04]
|
||||
|
|
@ -853,7 +861,7 @@ dest_io_apic_intin=16
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=1
|
||||
source_bus_id=0
|
||||
source_bus_irq=16
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -864,7 +872,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=0
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -875,7 +883,7 @@ dest_io_apic_intin=2
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=0
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -886,7 +894,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=1
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -897,7 +905,7 @@ dest_io_apic_intin=1
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=1
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -908,7 +916,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=3
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -919,7 +927,7 @@ dest_io_apic_intin=3
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=3
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -930,7 +938,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=4
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -941,7 +949,7 @@ dest_io_apic_intin=4
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=4
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -952,7 +960,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=5
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -963,7 +971,7 @@ dest_io_apic_intin=5
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=5
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -974,7 +982,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=6
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -985,7 +993,7 @@ dest_io_apic_intin=6
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=6
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -996,7 +1004,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=7
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1007,7 +1015,7 @@ dest_io_apic_intin=7
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=7
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1018,7 +1026,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=8
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1029,7 +1037,7 @@ dest_io_apic_intin=8
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=8
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1040,7 +1048,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=9
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1051,7 +1059,7 @@ dest_io_apic_intin=9
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=9
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1062,7 +1070,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=10
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1073,7 +1081,7 @@ dest_io_apic_intin=10
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=10
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1084,7 +1092,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=11
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1095,7 +1103,7 @@ dest_io_apic_intin=11
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=11
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1106,7 +1114,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=12
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1117,7 +1125,7 @@ dest_io_apic_intin=12
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=12
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1128,7 +1136,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=13
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1139,7 +1147,7 @@ dest_io_apic_intin=13
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=13
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1150,7 +1158,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=14
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1161,15 +1169,15 @@ dest_io_apic_intin=14
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=14
|
||||
trigger=ConformTrigger
|
||||
|
||||
[system.intel_mp_table.ext_entries]
|
||||
type=X86IntelMPBusHierarchy
|
||||
bus_id=0
|
||||
bus_id=1
|
||||
eventq_index=0
|
||||
parent_bus=1
|
||||
parent_bus=0
|
||||
subtractive_decode=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -1178,7 +1186,7 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
|
|
@ -1224,11 +1232,12 @@ sequential_access=false
|
|||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -1473,6 +1482,7 @@ HeaderType=0
|
|||
InterruptLine=14
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=9223372036854775808
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1763,8 +1773,33 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1773,6 +1808,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -1786,19 +1822,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
|
|||
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
|
||||
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
|
||||
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
|
||||
end_pfn_map = 1048576
|
||||
kernel direct mapping tables up to 100000000 @ 8000-d000
|
||||
|
|
@ -23,18 +24,18 @@ Setting APIC routing to flat
|
|||
Processors: 1
|
||||
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
|
||||
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
|
||||
Built 1 zonelists. Total pages: 30612
|
||||
Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
|
||||
Built 1 zonelists. Total pages: 30610
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 1999.999 MHz processor.
|
||||
time.c: Detected 2000.008 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
|
||||
Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
|
|
@ -44,7 +45,7 @@ ACPI: Core revision 20070126
|
|||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812524
|
||||
result 7812560
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
|
|
@ -56,6 +57,7 @@ usbcore: registered new interface driver usbfs
|
|||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
Time: tsc clocksource has been installed.
|
||||
|
|
|
|||
|
|
@ -263,8 +263,8 @@ transition_latency=100000000
|
|||
|
||||
[system.e820_table]
|
||||
type=X86E820Table
|
||||
children=entries0 entries1 entries2 entries3
|
||||
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
|
||||
children=entries0 entries1 entries2 entries3 entries4
|
||||
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
|
||||
eventq_index=0
|
||||
|
||||
[system.e820_table.entries0]
|
||||
|
|
@ -290,6 +290,13 @@ size=133169152
|
|||
|
||||
[system.e820_table.entries3]
|
||||
type=X86E820Entry
|
||||
addr=134217728
|
||||
eventq_index=0
|
||||
range_type=2
|
||||
size=3087007744
|
||||
|
||||
[system.e820_table.entries4]
|
||||
type=X86E820Entry
|
||||
addr=4294901760
|
||||
eventq_index=0
|
||||
range_type=2
|
||||
|
|
@ -350,13 +357,13 @@ version=17
|
|||
[system.intel_mp_table.base_entries03]
|
||||
type=X86IntelMPBus
|
||||
bus_id=0
|
||||
bus_type=ISA
|
||||
bus_type=PCI
|
||||
eventq_index=0
|
||||
|
||||
[system.intel_mp_table.base_entries04]
|
||||
type=X86IntelMPBus
|
||||
bus_id=1
|
||||
bus_type=PCI
|
||||
bus_type=ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.intel_mp_table.base_entries05]
|
||||
|
|
@ -366,7 +373,7 @@ dest_io_apic_intin=16
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=1
|
||||
source_bus_id=0
|
||||
source_bus_irq=16
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -377,7 +384,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=0
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -388,7 +395,7 @@ dest_io_apic_intin=2
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=0
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -399,7 +406,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=1
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -410,7 +417,7 @@ dest_io_apic_intin=1
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=1
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -421,7 +428,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=3
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -432,7 +439,7 @@ dest_io_apic_intin=3
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=3
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -443,7 +450,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=4
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -454,7 +461,7 @@ dest_io_apic_intin=4
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=4
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -465,7 +472,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=5
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -476,7 +483,7 @@ dest_io_apic_intin=5
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=5
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -487,7 +494,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=6
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -498,7 +505,7 @@ dest_io_apic_intin=6
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=6
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -509,7 +516,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=7
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -520,7 +527,7 @@ dest_io_apic_intin=7
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=7
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -531,7 +538,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=8
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -542,7 +549,7 @@ dest_io_apic_intin=8
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=8
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -553,7 +560,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=9
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -564,7 +571,7 @@ dest_io_apic_intin=9
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=9
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -575,7 +582,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=10
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -586,7 +593,7 @@ dest_io_apic_intin=10
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=10
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -597,7 +604,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=11
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -608,7 +615,7 @@ dest_io_apic_intin=11
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=11
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -619,7 +626,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=12
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -630,7 +637,7 @@ dest_io_apic_intin=12
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=12
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -641,7 +648,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=13
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -652,7 +659,7 @@ dest_io_apic_intin=13
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=13
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -663,7 +670,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=14
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -674,15 +681,15 @@ dest_io_apic_intin=14
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=14
|
||||
trigger=ConformTrigger
|
||||
|
||||
[system.intel_mp_table.ext_entries]
|
||||
type=X86IntelMPBusHierarchy
|
||||
bus_id=0
|
||||
bus_id=1
|
||||
eventq_index=0
|
||||
parent_bus=1
|
||||
parent_bus=0
|
||||
subtractive_decode=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -691,7 +698,7 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
|
|
@ -920,6 +927,7 @@ HeaderType=0
|
|||
InterruptLine=14
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=9223372036854775808
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1210,8 +1218,33 @@ pio=system.iobus.master[8]
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1220,6 +1253,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -1233,19 +1267,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
|
|||
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
|
||||
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
|
||||
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
|
||||
end_pfn_map = 1048576
|
||||
kernel direct mapping tables up to 100000000 @ 8000-d000
|
||||
|
|
@ -22,9 +23,9 @@ Processor #1
|
|||
I/O APIC #2 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 2
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
|
||||
Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
|
||||
PERCPU: Allocating 34160 bytes of per cpu data
|
||||
Built 1 zonelists. Total pages: 30615
|
||||
Built 1 zonelists. Total pages: 30613
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
|
|
@ -35,7 +36,7 @@ console handover: boot [earlyser0] -> real [ttyS0]
|
|||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 122004k/131072k available (3699k kernel code, 8516k reserved, 1767k data, 248k init)
|
||||
Memory: 121996k/131072k available (3699k kernel code, 8524k reserved, 1767k data, 248k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
|
|
@ -59,6 +60,7 @@ usbcore: registered new interface driver usbfs
|
|||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ type=Bridge
|
|||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
master=system.iobus.slave[0]
|
||||
|
|
@ -114,9 +114,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -353,6 +350,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu2.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -405,7 +403,6 @@ switched_out=true
|
|||
system=system
|
||||
tracer=system.cpu2.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=
|
||||
|
||||
|
|
@ -787,8 +784,8 @@ transition_latency=100000000
|
|||
|
||||
[system.e820_table]
|
||||
type=X86E820Table
|
||||
children=entries0 entries1 entries2 entries3
|
||||
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
|
||||
children=entries0 entries1 entries2 entries3 entries4
|
||||
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
|
||||
eventq_index=0
|
||||
|
||||
[system.e820_table.entries0]
|
||||
|
|
@ -814,6 +811,13 @@ size=133169152
|
|||
|
||||
[system.e820_table.entries3]
|
||||
type=X86E820Entry
|
||||
addr=134217728
|
||||
eventq_index=0
|
||||
range_type=2
|
||||
size=3087007744
|
||||
|
||||
[system.e820_table.entries4]
|
||||
type=X86E820Entry
|
||||
addr=4294901760
|
||||
eventq_index=0
|
||||
range_type=2
|
||||
|
|
@ -862,13 +866,13 @@ version=17
|
|||
[system.intel_mp_table.base_entries02]
|
||||
type=X86IntelMPBus
|
||||
bus_id=0
|
||||
bus_type=ISA
|
||||
bus_type=PCI
|
||||
eventq_index=0
|
||||
|
||||
[system.intel_mp_table.base_entries03]
|
||||
type=X86IntelMPBus
|
||||
bus_id=1
|
||||
bus_type=PCI
|
||||
bus_type=ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.intel_mp_table.base_entries04]
|
||||
|
|
@ -878,7 +882,7 @@ dest_io_apic_intin=16
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=1
|
||||
source_bus_id=0
|
||||
source_bus_irq=16
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -889,7 +893,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=0
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -900,7 +904,7 @@ dest_io_apic_intin=2
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=0
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -911,7 +915,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=1
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -922,7 +926,7 @@ dest_io_apic_intin=1
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=1
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -933,7 +937,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=3
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -944,7 +948,7 @@ dest_io_apic_intin=3
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=3
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -955,7 +959,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=4
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -966,7 +970,7 @@ dest_io_apic_intin=4
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=4
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -977,7 +981,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=5
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -988,7 +992,7 @@ dest_io_apic_intin=5
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=5
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -999,7 +1003,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=6
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1010,7 +1014,7 @@ dest_io_apic_intin=6
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=6
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1021,7 +1025,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=7
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1032,7 +1036,7 @@ dest_io_apic_intin=7
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=7
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1043,7 +1047,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=8
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1054,7 +1058,7 @@ dest_io_apic_intin=8
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=8
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1065,7 +1069,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=9
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1076,7 +1080,7 @@ dest_io_apic_intin=9
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=9
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1087,7 +1091,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=10
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1098,7 +1102,7 @@ dest_io_apic_intin=10
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=10
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1109,7 +1113,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=11
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1120,7 +1124,7 @@ dest_io_apic_intin=11
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=11
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1131,7 +1135,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=12
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1142,7 +1146,7 @@ dest_io_apic_intin=12
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=12
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1153,7 +1157,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=13
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1164,7 +1168,7 @@ dest_io_apic_intin=13
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=13
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1175,7 +1179,7 @@ dest_io_apic_intin=0
|
|||
eventq_index=0
|
||||
interrupt_type=ExtInt
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=14
|
||||
trigger=ConformTrigger
|
||||
|
||||
|
|
@ -1186,15 +1190,15 @@ dest_io_apic_intin=14
|
|||
eventq_index=0
|
||||
interrupt_type=INT
|
||||
polarity=ConformPolarity
|
||||
source_bus_id=0
|
||||
source_bus_id=1
|
||||
source_bus_irq=14
|
||||
trigger=ConformTrigger
|
||||
|
||||
[system.intel_mp_table.ext_entries]
|
||||
type=X86IntelMPBusHierarchy
|
||||
bus_id=0
|
||||
bus_id=1
|
||||
eventq_index=0
|
||||
parent_bus=1
|
||||
parent_bus=0
|
||||
subtractive_decode=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -1203,7 +1207,7 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
|
|
@ -1284,11 +1288,12 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -1533,6 +1538,7 @@ HeaderType=0
|
|||
InterruptLine=14
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=9223372036854775808
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1823,8 +1829,33 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -1833,6 +1864,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -1846,19 +1878,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -1888,10 +1927,11 @@ vendor=
|
|||
version=
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
|
|||
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
|
||||
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
|
||||
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
|
||||
end_pfn_map = 1048576
|
||||
kernel direct mapping tables up to 100000000 @ 8000-d000
|
||||
|
|
@ -23,18 +24,18 @@ Setting APIC routing to flat
|
|||
Processors: 1
|
||||
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
|
||||
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
|
||||
Built 1 zonelists. Total pages: 30612
|
||||
Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
|
||||
Built 1 zonelists. Total pages: 30610
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 1999.986 MHz processor.
|
||||
time.c: Detected 2000.002 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
|
||||
Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
|
|
@ -44,7 +45,7 @@ ACPI: Core revision 20070126
|
|||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812464
|
||||
result 7812527
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
|
|
@ -56,6 +57,7 @@ usbcore: registered new interface driver usbfs
|
|||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
Time: tsc clocksource has been installed.
|
||||
|
|
|
|||
|
|
@ -16,10 +16,10 @@ cache_line_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hypervisor_addr=1099243257856
|
||||
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
|
||||
hypervisor_bin=/scratch/nilay/GEM5/system/binaries/q_new.bin
|
||||
hypervisor_desc=system.hypervisor_desc
|
||||
hypervisor_desc_addr=133446500352
|
||||
hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
|
||||
hypervisor_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-hv.bin
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
|
|
@ -27,19 +27,19 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=atomic
|
||||
mem_ranges=1048576:68157439 2147483648:2415919103
|
||||
memories=system.hypervisor_desc system.physmem1 system.partition_desc system.physmem0 system.rom system.nvram
|
||||
memories=system.nvram system.physmem1 system.hypervisor_desc system.partition_desc system.physmem0 system.rom
|
||||
num_work_ids=16
|
||||
nvram=system.nvram
|
||||
nvram_addr=133429198848
|
||||
nvram_bin=/dist/m5/system/binaries/nvram1
|
||||
nvram_bin=/scratch/nilay/GEM5/system/binaries/nvram1
|
||||
openboot_addr=1099243716608
|
||||
openboot_bin=/dist/m5/system/binaries/openboot_new.bin
|
||||
openboot_bin=/scratch/nilay/GEM5/system/binaries/openboot_new.bin
|
||||
partition_desc=system.partition_desc
|
||||
partition_desc_addr=133445976064
|
||||
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
|
||||
readfile=/z/stever/hg/gem5/tests/halt.sh
|
||||
partition_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-md.bin
|
||||
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
||||
reset_addr=1099243192320
|
||||
reset_bin=/dist/m5/system/binaries/reset_new.bin
|
||||
reset_bin=/scratch/nilay/GEM5/system/binaries/reset_new.bin
|
||||
rom=system.rom
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -160,7 +160,7 @@ table_size=65536
|
|||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/dist/m5/system/disks/disk.s10hw2
|
||||
image_file=/scratch/nilay/GEM5/system/disks/disk.s10hw2
|
||||
read_only=true
|
||||
|
||||
[system.dvfs_handler]
|
||||
|
|
|
|||
|
|
@ -471,7 +471,7 @@
|
|||
}
|
||||
},
|
||||
"symbolfile": "",
|
||||
"readfile": "/z/stever/hg/gem5/tests/halt.sh",
|
||||
"readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh",
|
||||
"hypervisor_addr": 1099243257856,
|
||||
"mem_ranges": [
|
||||
"1048576:68157439",
|
||||
|
|
@ -479,17 +479,17 @@
|
|||
],
|
||||
"cxx_class": "SparcSystem",
|
||||
"load_offset": 0,
|
||||
"reset_bin": "/dist/m5/system/binaries/reset_new.bin",
|
||||
"reset_bin": "/scratch/nilay/GEM5/system/binaries/reset_new.bin",
|
||||
"openboot_addr": 1099243716608,
|
||||
"work_end_ckpt_count": 0,
|
||||
"nvram_addr": 133429198848,
|
||||
"memories": [
|
||||
"system.hypervisor_desc",
|
||||
"system.nvram",
|
||||
"system.physmem1",
|
||||
"system.hypervisor_desc",
|
||||
"system.partition_desc",
|
||||
"system.physmem0",
|
||||
"system.rom",
|
||||
"system.nvram"
|
||||
"system.rom"
|
||||
],
|
||||
"work_begin_ckpt_count": 0,
|
||||
"partition_desc": {
|
||||
|
|
@ -639,8 +639,8 @@
|
|||
"type": "DVFSHandler"
|
||||
},
|
||||
"work_end_exit_count": 0,
|
||||
"hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin",
|
||||
"openboot_bin": "/dist/m5/system/binaries/openboot_new.bin",
|
||||
"hypervisor_desc_bin": "/scratch/nilay/GEM5/system/binaries/1up-hv.bin",
|
||||
"openboot_bin": "/scratch/nilay/GEM5/system/binaries/openboot_new.bin",
|
||||
"voltage_domain": {
|
||||
"name": "voltage_domain",
|
||||
"eventq_index": 0,
|
||||
|
|
@ -700,7 +700,7 @@
|
|||
"work_cpus_ckpt_count": 0,
|
||||
"work_begin_exit_count": 0,
|
||||
"path": "system",
|
||||
"hypervisor_bin": "/dist/m5/system/binaries/q_new.bin",
|
||||
"hypervisor_bin": "/scratch/nilay/GEM5/system/binaries/q_new.bin",
|
||||
"cpu_clk_domain": {
|
||||
"name": "cpu_clk_domain",
|
||||
"clock": [
|
||||
|
|
@ -714,12 +714,12 @@
|
|||
"type": "SrcClockDomain",
|
||||
"domain_id": -1
|
||||
},
|
||||
"nvram_bin": "/dist/m5/system/binaries/nvram1",
|
||||
"nvram_bin": "/scratch/nilay/GEM5/system/binaries/nvram1",
|
||||
"mem_mode": "atomic",
|
||||
"name": "system",
|
||||
"init_param": 0,
|
||||
"type": "SparcSystem",
|
||||
"partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin",
|
||||
"partition_desc_bin": "/scratch/nilay/GEM5/system/binaries/1up-md.bin",
|
||||
"load_addr_mask": 1099511627775,
|
||||
"cpu": {
|
||||
"do_statistics_insts": true,
|
||||
|
|
@ -825,7 +825,7 @@
|
|||
"eventq_index": 0,
|
||||
"cxx_class": "RawDiskImage",
|
||||
"path": "system.disk0.image.child",
|
||||
"image_file": "/dist/m5/system/disks/disk.s10hw2",
|
||||
"image_file": "/scratch/nilay/GEM5/system/disks/disk.s10hw2",
|
||||
"type": "RawDiskImage"
|
||||
},
|
||||
"path": "system.disk0.image",
|
||||
|
|
|
|||
|
|
@ -730,10 +730,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -763,6 +764,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -803,6 +831,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -816,19 +845,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -65,19 +65,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -97,20 +98,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -128,7 +129,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -149,7 +149,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -162,17 +162,17 @@ forward_snoops=true
|
|||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
|
|
@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
|
|||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
|
|
@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -249,10 +249,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -264,275 +264,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -542,18 +500,18 @@ assoc=2
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -565,9 +523,9 @@ assoc=2
|
|||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
|
@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -712,6 +688,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -752,6 +755,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -765,19 +769,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -70,9 +70,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -223,6 +220,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -299,10 +299,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -332,6 +333,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -124,6 +121,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -200,10 +200,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -233,6 +234,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -126,7 +127,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -614,10 +614,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -647,6 +648,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -687,6 +715,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -700,19 +729,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -158,6 +155,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -234,10 +234,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -267,6 +268,7 @@ ppid=99
|
|||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -632,10 +632,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -665,6 +666,7 @@ ppid=99
|
|||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -705,6 +733,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -718,19 +747,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -730,10 +730,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -763,6 +764,7 @@ ppid=99
|
|||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -803,6 +831,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -816,19 +845,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -65,19 +65,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -97,20 +98,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -128,7 +129,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -149,7 +149,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -162,17 +162,17 @@ forward_snoops=true
|
|||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
|
|
@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
|
|||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
|
|
@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -249,10 +249,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -264,275 +264,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -542,18 +500,18 @@ assoc=2
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -565,9 +523,9 @@ assoc=2
|
|||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
|
@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -712,6 +688,7 @@ ppid=99
|
|||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -752,6 +755,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -765,19 +769,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -70,9 +70,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -223,6 +220,7 @@ ppid=99
|
|||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -299,10 +299,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -332,6 +333,7 @@ ppid=99
|
|||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -126,7 +127,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -614,10 +614,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -647,6 +648,7 @@ ppid=99
|
|||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -687,6 +715,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -700,19 +729,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -158,6 +155,7 @@ ppid=99
|
|||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -234,10 +234,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -267,6 +268,7 @@ ppid=99
|
|||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -632,10 +632,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -665,6 +666,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -705,6 +733,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -718,19 +747,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ clk_domain=system.clk_domain
|
|||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
|
|
@ -73,6 +74,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -125,7 +127,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -580,10 +581,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -603,7 +605,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -613,6 +615,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -653,6 +682,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -666,19 +696,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -125,6 +122,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -201,10 +201,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -234,6 +235,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -730,10 +730,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -763,6 +764,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -803,6 +831,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -816,19 +845,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -65,19 +65,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -97,20 +98,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -128,7 +129,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -149,7 +149,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -162,17 +162,17 @@ forward_snoops=true
|
|||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
|
|
@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
|
|||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
|
|
@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -249,10 +249,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -264,275 +264,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -542,18 +500,18 @@ assoc=2
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -565,9 +523,9 @@ assoc=2
|
|||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
|
@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -712,6 +688,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -752,6 +755,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -765,19 +769,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -70,9 +70,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -223,6 +220,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -299,10 +299,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -332,6 +333,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -632,10 +632,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -648,7 +649,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cmd=perlbmk -I. -I lib mdred.makerand.pl
|
||||
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
|
||||
egid=100
|
||||
env=
|
||||
|
|
@ -665,6 +666,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -705,6 +733,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -718,19 +747,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ clk_domain=system.clk_domain
|
|||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
|
|
@ -73,6 +74,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -125,7 +127,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -580,10 +581,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -596,14 +598,14 @@ eventq_index=0
|
|||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cmd=perlbmk -I. -I lib mdred.makerand.pl
|
||||
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -613,6 +615,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -653,6 +682,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -666,19 +696,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -108,7 +105,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cmd=perlbmk -I. -I lib mdred.makerand.pl
|
||||
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
|
|
@ -125,6 +122,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -201,10 +201,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -217,7 +218,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cmd=perlbmk -I. -I lib mdred.makerand.pl
|
||||
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
|
|
@ -234,6 +235,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -730,10 +730,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -746,7 +747,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cmd=perlbmk -I. -I lib mdred.makerand.pl
|
||||
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
|
||||
egid=100
|
||||
env=
|
||||
|
|
@ -763,6 +764,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -803,6 +831,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -816,19 +845,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -65,19 +65,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -97,20 +98,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -128,7 +129,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -149,7 +149,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -162,17 +162,17 @@ forward_snoops=true
|
|||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
|
|
@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
|
|||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
|
|
@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -249,10 +249,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -264,275 +264,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -542,18 +500,18 @@ assoc=2
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -565,9 +523,9 @@ assoc=2
|
|||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
|
@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -695,7 +671,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cmd=perlbmk -I. -I lib mdred.makerand.pl
|
||||
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
|
|
@ -712,6 +688,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -752,6 +755,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -765,19 +769,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.407884 # Nu
|
|||
sim_ticks 407883784500 # Number of ticks simulated
|
||||
final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 91837 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 113063 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 58469822 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 2565440 # Number of bytes of host memory used
|
||||
host_seconds 6975.97 # Real time elapsed on the host
|
||||
host_inst_rate 65117 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 80168 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41458433 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 2600432 # Number of bytes of host memory used
|
||||
host_seconds 9838.38 # Real time elapsed on the host
|
||||
sim_insts 640649298 # Number of instructions simulated
|
||||
sim_ops 788724957 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -420,7 +420,7 @@ system.cpu.numCycles 815767570 # nu
|
|||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Insts 1200075862 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked
|
||||
|
|
|
|||
|
|
@ -70,9 +70,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -206,7 +203,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cmd=perlbmk -I. -I lib mdred.makerand.pl
|
||||
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
|
|
@ -223,6 +220,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -299,10 +299,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -315,7 +316,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cmd=perlbmk -I. -I lib mdred.makerand.pl
|
||||
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
|
|
@ -332,6 +333,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -632,10 +632,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -665,6 +666,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -705,6 +733,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -718,19 +747,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ clk_domain=system.clk_domain
|
|||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
|
|
@ -73,6 +74,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -125,7 +127,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -580,10 +581,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -603,7 +605,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -613,6 +615,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -653,6 +682,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -666,19 +696,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -125,6 +122,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -201,10 +201,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -234,6 +235,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -730,10 +730,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -763,6 +764,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -803,6 +831,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -816,19 +845,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -65,19 +65,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -97,20 +98,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -128,7 +129,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -149,7 +149,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -162,17 +162,17 @@ forward_snoops=true
|
|||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
|
|
@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
|
|||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
|
|
@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -249,10 +249,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -264,275 +264,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -542,18 +500,18 @@ assoc=2
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -565,9 +523,9 @@ assoc=2
|
|||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
|
@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -712,6 +688,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -752,6 +755,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -765,19 +769,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -70,9 +70,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -223,6 +220,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -299,10 +299,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -332,6 +333,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -124,6 +121,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -200,10 +200,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -233,6 +234,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -632,10 +632,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -665,6 +666,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -705,6 +733,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -718,19 +747,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ clk_domain=system.clk_domain
|
|||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
|
|
@ -73,6 +74,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -125,7 +127,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -580,10 +581,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -603,7 +605,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -613,6 +615,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -653,6 +682,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -666,19 +696,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -125,6 +122,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -201,10 +201,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -234,6 +235,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -730,10 +730,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -763,6 +764,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -803,6 +831,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -816,19 +845,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -65,19 +65,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -97,20 +98,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -128,7 +129,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -149,7 +149,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -162,17 +162,17 @@ forward_snoops=true
|
|||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
|
|
@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
|
|||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
|
|
@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -249,10 +249,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -264,275 +264,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -542,18 +500,18 @@ assoc=2
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -565,9 +523,9 @@ assoc=2
|
|||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
|
@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -712,6 +688,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -752,6 +755,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -765,19 +769,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -70,9 +70,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -223,6 +220,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -299,10 +299,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -332,6 +333,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -158,6 +155,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -234,10 +234,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -267,6 +268,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -632,10 +632,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -665,6 +666,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -705,6 +733,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -718,19 +747,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ clk_domain=system.clk_domain
|
|||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
|
|
@ -73,6 +74,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -125,7 +127,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -580,10 +581,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -603,7 +605,7 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -613,6 +615,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -653,6 +682,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -666,19 +696,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -125,6 +122,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -201,10 +201,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -234,6 +235,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -730,10 +730,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -763,6 +764,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -803,6 +831,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -816,19 +845,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
0
tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr
Normal file → Executable file
0
tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr
Normal file → Executable file
0
tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
Normal file → Executable file
0
tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
Normal file → Executable file
|
|
@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
|
|||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
|
|
@ -65,19 +65,20 @@ commitToRenameDelay=1
|
|||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
dispatchWidth=8
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchToDecodeDelay=1
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
|
|
@ -97,20 +98,20 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=0
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
|
|
@ -128,7 +129,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
|
|
@ -149,7 +149,7 @@ localCtrBits=2
|
|||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
predType=bi-mode
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -162,17 +162,17 @@ forward_snoops=true
|
|||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
|
|
@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
|
|||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
size=32768
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
|
|
@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
|
|
@ -249,10 +249,10 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -264,275 +264,233 @@ opLat=3
|
|||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=19
|
||||
issueLat=12
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList
|
||||
opList=system.cpu.fuPool.FUList2.opList
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList]
|
||||
[system.cpu.fuPool.FUList2.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
opList=system.cpu.fuPool.FUList3.opList
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
[system.cpu.fuPool.FUList3.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=9
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=33
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -542,18 +500,18 @@ assoc=2
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -565,9 +523,9 @@ assoc=2
|
|||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=131072
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
|
@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
size=1048576
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -712,6 +688,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -752,6 +755,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -765,19 +769,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -70,9 +70,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -223,6 +220,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -299,10 +299,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -332,6 +333,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -124,6 +121,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -200,10 +200,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -233,6 +234,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
|
|
@ -126,7 +127,6 @@ switched_out=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -614,10 +614,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -647,6 +648,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -687,6 +715,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -700,19 +729,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
|
|||
|
|
@ -68,9 +68,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -158,6 +155,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -234,10 +234,11 @@ sequential_access=false
|
|||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -267,6 +268,7 @@ ppid=99
|
|||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
|
|
@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
|
|||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
|
|||
|
|
@ -84,9 +84,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -217,9 +214,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -393,7 +387,7 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
|
|
@ -474,11 +468,12 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -539,10 +534,11 @@ output=true
|
|||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -611,6 +607,7 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1066,6 +1063,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
|
|||
|
|
@ -84,9 +84,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -224,10 +221,11 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -306,7 +304,7 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
|
|
@ -352,11 +350,12 @@ sequential_access=false
|
|||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -478,6 +477,7 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -933,6 +933,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
|
|||
|
|
@ -379,7 +379,7 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
|
|
@ -460,11 +460,12 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -492,8 +493,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -502,6 +528,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -515,19 +542,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -555,10 +589,11 @@ output=true
|
|||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -627,6 +662,7 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -1082,6 +1118,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
|
|||
|
|
@ -217,10 +217,11 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -299,7 +300,7 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
|
|
@ -345,11 +346,12 @@ sequential_access=false
|
|||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -377,8 +379,33 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
|
|
@ -387,6 +414,7 @@ conf_table_reported=true
|
|||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
max_accesses_per_row=16
|
||||
|
|
@ -400,19 +428,26 @@ read_buffer_size=32
|
|||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
|
|
@ -501,6 +536,7 @@ HeaderType=0
|
|||
InterruptLine=30
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -956,6 +992,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ load_offset=0
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
|
@ -124,9 +124,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -143,14 +140,14 @@ icache_port=system.cpu0.icache.cpu_side
|
|||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -158,15 +155,15 @@ sequential_access=false
|
|||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
mem_side=system.cpu0.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
|
@ -196,7 +193,7 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[5]
|
||||
port=system.cpu0.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -213,40 +210,40 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
port=system.cpu0.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
mem_side=system.cpu0.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -305,7 +302,7 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[4]
|
||||
port=system.cpu0.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -322,7 +319,71 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
port=system.cpu0.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu0.l2cache]
|
||||
type=BaseCache
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu0.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu0.l2cache.tags
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.toL2Bus.master[0]
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu0.l2cache.tags]
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
|
||||
[system.cpu0.toL2Bus]
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu0.l2cache.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -330,7 +391,7 @@ eventq_index=0
|
|||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
|
@ -355,9 +416,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -374,14 +432,14 @@ icache_port=system.cpu1.icache.cpu_side
|
|||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=6
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -389,15 +447,15 @@ sequential_access=false
|
|||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
write_buffers=16
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
mem_side=system.cpu1.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu1.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
|
@ -427,7 +485,7 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[11]
|
||||
port=system.cpu1.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -444,40 +502,40 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[9]
|
||||
port=system.cpu1.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
mshrs=2
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.icache.tags
|
||||
tgts_per_mshr=20
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
mem_side=system.cpu1.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu1.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
hit_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -536,7 +594,7 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[10]
|
||||
port=system.cpu1.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -553,7 +611,71 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[8]
|
||||
port=system.cpu1.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu1.l2cache]
|
||||
type=BaseCache
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=12
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=16
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu1.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tags=system.cpu1.l2cache.tags
|
||||
tgts_per_mshr=8
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.toL2Bus.master[0]
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu1.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
sys=system
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu1.l2cache.tags]
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
|
||||
[system.cpu1.toL2Bus]
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu1.l2cache.cpu_side
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -581,13 +703,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -612,7 +734,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -661,11 +783,12 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -706,12 +829,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -766,6 +889,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -850,6 +974,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -1168,15 +1302,16 @@ output=true
|
|||
port=3456
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
|
|
|
|||
|
|
@ -124,9 +124,6 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -360,10 +357,11 @@ sequential_access=false
|
|||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -396,13 +394,13 @@ eventq_index=0
|
|||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
||||
|
||||
[system.iocache]
|
||||
|
|
@ -427,7 +425,7 @@ tags=system.iocache.tags
|
|||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
cpu_side=system.iobus.master[26]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
|
|
@ -441,11 +439,12 @@ sequential_access=false
|
|||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=Null
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -486,12 +485,12 @@ port=system.membus.master[6]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
max_mem_size=268435456
|
||||
mem_start_addr=0
|
||||
pci_cfg_base=0
|
||||
pci_cfg_gen_offsets=false
|
||||
pci_io_base=0
|
||||
system=system
|
||||
|
||||
[system.realview.a9scu]
|
||||
|
|
@ -546,6 +545,7 @@ HeaderType=0
|
|||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
LegacyIOBase=0
|
||||
MSICAPBaseOffset=0
|
||||
MSICAPCapId=0
|
||||
MSICAPMaskBits=0
|
||||
|
|
@ -630,6 +630,16 @@ pio_latency=100000
|
|||
system=system
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
pio_addr=268496896
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue