From 1e70401c08c5976b9ef01b95e100625bdbaf5f3d Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:20:19 -0800
Subject: [PATCH] X86: Fix a few bugs with the segment register instructions in
 real mode. Fix a few instances where the register form of zext was used where
 zexti was intended. Also get rid of the 64 bit only rip relative addressed
 version since 64 bit and real mode are mutually exclusive.

---
 .../isa/insts/general_purpose/data_transfer/move.py   | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index 0e3e9f270..82c076216 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -215,7 +215,7 @@ def macroop MOV_P_S {
 };
 
 def macroop MOV_REAL_S_R {
-    zext t2, regm, 15, dataSize=8
+    zexti t2, regm, 15, dataSize=8
     slli t3, t2, 2, dataSize=8
     wrsel reg, regm
     wrbase reg, t3
@@ -223,19 +223,14 @@ def macroop MOV_REAL_S_R {
 
 def macroop MOV_REAL_S_M {
     ld t1, seg, sib, disp, dataSize=2
-    zext t2, t1, 15, dataSize=8
+    zexti t2, t1, 15, dataSize=8
     slli t3, t2, 2, dataSize=8
     wrsel reg, t1
     wrbase reg, t3
 };
 
 def macroop MOV_REAL_S_P {
-    rdip t7
-    ld t1, seg, riprel, disp, dataSize=2
-    zext t2, t1, 15, dataSize=8
-    slli t3, t2, 2, dataSize=8
-    wrsel reg, t1
-    wrbase reg, t3
+    panic "RIP relative addressing shouldn't happen in real mode"
 };
 
 def macroop MOV_S_R {