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ARM: More accurately describe the effects of using the control operands.

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Gabe Black 2009-11-14 19:22:29 -08:00
parent 50b9149c75
commit 1df0025e28
1 changed files with 6 additions and 6 deletions
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12
src/arch/arm/isa/operands.isa
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@ -81,12 +81,12 @@ def operands {{
#Memory Operand #Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', 'IsInteger', 41), 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', (None, None, 'IsControl'), 41),
'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 42), 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', (None, None, 'IsControl'), 42),
'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 43), 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', (None, None, 'IsControl'), 43),
'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 44), 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', (None, None, 'IsControl'), 44),
'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 45), 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', (None, None, 'IsControl'), 45),
'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50), 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50),
'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51) 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51)