mem: Add DRAM low-power functionality
Added power-down state transitions to the DRAM controller model. Added per rank parameter, outstandingEvents, which tracks the number of outstanding command events and is used to determine when the controller should transition to a low power state. The controller will only transition when there are no outstanding events scheduled and the number of command entries for the given rank is 0. The outstandingEvents parameter is incremented for every RD/WR burst, PRE, and REF event scheduled. ACT is implicitly covered by RD/WR since burst will always issue and complete after a required ACT. The parameter is decremented when the event is serviced (completed). The controller will automatically transition to ACT power down, PRE power down, or SREF. Transition to ACT power down state scheduled from: 1) The RespondEvent, where read data is received from the memory. ACT power-down entry will be scheduled when one or more banks is open, all commands for the rank have completed (no more commands scheduled), and there are no commands in queue for the rank Transition to PRE power down scheduled from: 1) respondEvent, when all banks are closed, all commands have completed, and there are no commands in queue for the rank 2) prechargeEvent when all banks are closed, all commands have completed, and there are no commands in queue for the rank 3) refreshEvent, after the refresh is complete when the previous state was ACT power-down 4) refreshEvent, after the refresh is complete when the previous state was PRE power-down and there are commands in the queue. Transition to SREF will be scheduled from: 1) refreshEvent, after the refresh is completes when the previous state was PRE power-down with no commands in queue Power-down exit commands are scheduled from: 1) The refreshEvent, prior to issuing a refresh 2) doDRAMAccess, to wake-up the rank for RD/WR command issue. Self-refresh exit commands are scheduled from: 1) The next request event, when the queue has commands for the rank in the readQueue or there are commands for the rank in the writeQueue and the bus state is WRITE. Change-Id: I6103f660776e36c686655e71d92ec7b5b752050a Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
This commit is contained in:
Wendy Elsasser
parent
7b269f2c95
commit
1dc16aff24
2 changed files with 719 additions and 136 deletions
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@ -41,6 +41,7 @@
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* Ani Udipi
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* Neha Agarwal
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* Omar Naji
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* Wendy Elsasser
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*/
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#include "base/bitfield.hh"
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@ -60,6 +61,7 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
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port(name() + ".port", *this), isTimingMode(false),
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retryRdReq(false), retryWrReq(false),
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busState(READ),
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busStateNext(READ),
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nextReqEvent(this), respondEvent(this),
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deviceSize(p->device_size),
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deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
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@ -481,6 +483,9 @@ DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
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readQueue.push_back(dram_pkt);
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// increment read entries of the rank
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++dram_pkt->rankRef.readEntries;
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// Update stats
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avgRdQLen = readQueue.size() + respQueue.size();
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}
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@ -544,6 +549,9 @@ DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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// Update stats
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avgWrQLen = writeQueue.size();
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// increment write entries of the rank
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++dram_pkt->rankRef.writeEntries;
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} else {
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DPRINTF(DRAM, "Merging write burst with existing queue entry\n");
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@ -656,6 +664,47 @@ DRAMCtrl::processRespondEvent()
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DRAMPacket* dram_pkt = respQueue.front();
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// if a read has reached its ready-time, decrement the number of reads
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// At this point the packet has been handled and there is a possibility
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// to switch to low-power mode if no other packet is available
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--dram_pkt->rankRef.readEntries;
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DPRINTF(DRAM, "number of read entries for rank %d is %d\n",
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dram_pkt->rank, dram_pkt->rankRef.readEntries);
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// counter should at least indicate one outstanding request
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// for this read
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assert(dram_pkt->rankRef.outstandingEvents > 0);
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// read response received, decrement count
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--dram_pkt->rankRef.outstandingEvents;
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// at this moment should be either ACT or IDLE depending on
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// if PRE has occurred to close all banks
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assert((dram_pkt->rankRef.pwrState == PWR_ACT) ||
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(dram_pkt->rankRef.pwrState == PWR_IDLE));
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// track if this is the last packet before idling
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// and that there are no outstanding commands to this rank
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if (dram_pkt->rankRef.lowPowerEntryReady()) {
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// verify that there are no events scheduled
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assert(!dram_pkt->rankRef.activateEvent.scheduled());
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assert(!dram_pkt->rankRef.prechargeEvent.scheduled());
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assert(dram_pkt->rankRef.refreshState == REF_IDLE);
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// if coming from active state, schedule power event to
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// active power-down else go to precharge power-down
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DPRINTF(DRAMState, "Rank %d sleep at tick %d; current power state is "
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"%d\n", dram_pkt->rank, curTick(), dram_pkt->rankRef.pwrState);
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// default to ACT power-down unless already in IDLE state
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// could be in IDLE if PRE issued before data returned
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PowerState next_pwr_state = PWR_ACT_PDN;
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if (dram_pkt->rankRef.pwrState == PWR_IDLE) {
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next_pwr_state = PWR_PRE_PDN;
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}
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dram_pkt->rankRef.powerDownSleep(next_pwr_state, curTick());
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}
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if (dram_pkt->burstHelper) {
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// it is a split packet
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dram_pkt->burstHelper->burstsServiced++;
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@ -1012,10 +1061,13 @@ DRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace)
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// would have reached the idle state, so schedule an event and
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// rather check once we actually make it to the point in time when
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// the (last) precharge takes place
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if (!rank_ref.prechargeEvent.scheduled())
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if (!rank_ref.prechargeEvent.scheduled()) {
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schedule(rank_ref.prechargeEvent, pre_done_at);
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else if (rank_ref.prechargeEvent.when() < pre_done_at)
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// New event, increment count
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++rank_ref.outstandingEvents;
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} else if (rank_ref.prechargeEvent.when() < pre_done_at) {
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reschedule(rank_ref.prechargeEvent, pre_done_at);
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}
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}
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void
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@ -1027,6 +1079,14 @@ DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
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// get the rank
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Rank& rank = dram_pkt->rankRef;
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// are we in or transitioning to a low-power state and have not scheduled
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// a power-up event?
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// if so, wake up from power down to issue RD/WR burst
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if (rank.inLowPowerState) {
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assert(rank.pwrState != PWR_SREF);
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rank.scheduleWakeUpEvent(tXP);
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}
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// get the bank
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Bank& bank = dram_pkt->bankRef;
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@ -1229,12 +1289,33 @@ DRAMCtrl::processNextReqEvent()
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int busyRanks = 0;
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for (auto r : ranks) {
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if (!r->isAvailable()) {
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// rank is busy refreshing
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busyRanks++;
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if (r->pwrState != PWR_SREF) {
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// rank is busy refreshing
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DPRINTF(DRAMState, "Rank %d is not available\n", r->rank);
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busyRanks++;
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// let the rank know that if it was waiting to drain, it
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// is now done and ready to proceed
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r->checkDrainDone();
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// let the rank know that if it was waiting to drain, it
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// is now done and ready to proceed
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r->checkDrainDone();
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}
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// check if we were in self-refresh and haven't started
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// to transition out
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if ((r->pwrState == PWR_SREF) && r->inLowPowerState) {
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DPRINTF(DRAMState, "Rank %d is in self-refresh\n", r->rank);
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// if we have commands queued to this rank and we don't have
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// a minimum number of active commands enqueued,
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// exit self-refresh
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if (r->forceSelfRefreshExit()) {
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DPRINTF(DRAMState, "rank %d was in self refresh and"
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" should wake up\n", r->rank);
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//wake up from self-refresh
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r->scheduleWakeUpEvent(tXS);
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// things are brought back into action once a refresh is
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// performed after self-refresh
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// continue with selection for other ranks
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}
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}
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}
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}
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@ -1245,30 +1326,32 @@ DRAMCtrl::processNextReqEvent()
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return;
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}
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// pre-emptively set to false. Overwrite if in READ_TO_WRITE
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// or WRITE_TO_READ state
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// pre-emptively set to false. Overwrite if in transitioning to
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// a new state
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bool switched_cmd_type = false;
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if (busState == READ_TO_WRITE) {
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DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
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"waiting\n", readsThisTime, readQueue.size());
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if (busState != busStateNext) {
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if (busState == READ) {
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DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
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"waiting\n", readsThisTime, readQueue.size());
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// sample and reset the read-related stats as we are now
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// transitioning to writes, and all reads are done
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rdPerTurnAround.sample(readsThisTime);
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readsThisTime = 0;
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// sample and reset the read-related stats as we are now
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// transitioning to writes, and all reads are done
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rdPerTurnAround.sample(readsThisTime);
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readsThisTime = 0;
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// now proceed to do the actual writes
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busState = WRITE;
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switched_cmd_type = true;
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} else if (busState == WRITE_TO_READ) {
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DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
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"waiting\n", writesThisTime, writeQueue.size());
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// now proceed to do the actual writes
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switched_cmd_type = true;
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} else {
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DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
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"waiting\n", writesThisTime, writeQueue.size());
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wrPerTurnAround.sample(writesThisTime);
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writesThisTime = 0;
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wrPerTurnAround.sample(writesThisTime);
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writesThisTime = 0;
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busState = READ;
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switched_cmd_type = true;
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switched_cmd_type = true;
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}
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// update busState to match next state until next transition
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busState = busStateNext;
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}
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// when we get here it is either a read or a write
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@ -1323,6 +1406,7 @@ DRAMCtrl::processNextReqEvent()
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DRAMPacket* dram_pkt = readQueue.front();
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assert(dram_pkt->rankRef.isAvailable());
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// here we get a bit creative and shift the bus busy time not
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// just the tWTR, but also a CAS latency to capture the fact
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// that we are allowed to prepare a new bank, but not issue a
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@ -1337,6 +1421,9 @@ DRAMCtrl::processNextReqEvent()
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// At this point we're done dealing with the request
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readQueue.pop_front();
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// Every respQueue which will generate an event, increment count
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++dram_pkt->rankRef.outstandingEvents;
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// sanity check
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assert(dram_pkt->size <= burstSize);
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assert(dram_pkt->readyTime >= curTick());
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@ -1364,7 +1451,7 @@ DRAMCtrl::processNextReqEvent()
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// draining), or because the writes hit the hight threshold
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if (switch_to_writes) {
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// transition to writing
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busState = READ_TO_WRITE;
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busStateNext = WRITE;
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}
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} else {
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// bool to check if write to free rank is found
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@ -1398,6 +1485,26 @@ DRAMCtrl::processNextReqEvent()
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doDRAMAccess(dram_pkt);
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writeQueue.pop_front();
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// removed write from queue, decrement count
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--dram_pkt->rankRef.writeEntries;
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// Schedule write done event to decrement event count
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// after the readyTime has been reached
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// Only schedule latest write event to minimize events
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// required; only need to ensure that final event scheduled covers
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// the time that writes are outstanding and bus is active
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// to holdoff power-down entry events
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if (!dram_pkt->rankRef.writeDoneEvent.scheduled()) {
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schedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime);
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// New event, increment count
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++dram_pkt->rankRef.outstandingEvents;
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} else if (dram_pkt->rankRef.writeDoneEvent.when() <
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dram_pkt-> readyTime) {
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reschedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime);
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}
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isInWriteQueue.erase(burstAlign(dram_pkt->addr));
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delete dram_pkt;
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@ -1410,7 +1517,7 @@ DRAMCtrl::processNextReqEvent()
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drainState() != DrainState::Draining) ||
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(!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
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// turn the bus back around for reads again
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busState = WRITE_TO_READ;
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busStateNext = READ;
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// note that the we switch back to reads also in the idle
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// case, which eventually will check for any draining and
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@ -1518,11 +1625,13 @@ DRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue,
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DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p)
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: EventManager(&_memory), memory(_memory),
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pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0),
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refreshState(REF_IDLE), refreshDueAt(0),
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power(_p, false), numBanksActive(0),
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activateEvent(*this), prechargeEvent(*this),
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refreshEvent(*this), powerEvent(*this)
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pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE),
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pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE),
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refreshState(REF_IDLE), inLowPowerState(false), rank(0),
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readEntries(0), writeEntries(0), outstandingEvents(0),
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wakeUpAllowedAt(0), power(_p, false), numBanksActive(0),
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writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this),
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refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this)
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{ }
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void
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@ -1544,6 +1653,27 @@ DRAMCtrl::Rank::suspend()
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// Update the stats
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updatePowerStats();
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// don't automatically transition back to LP state after next REF
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pwrStatePostRefresh = PWR_IDLE;
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}
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bool
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DRAMCtrl::Rank::lowPowerEntryReady() const
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{
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bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries == 0))
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|| ((memory.busStateNext == WRITE) &&
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(writeEntries == 0));
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if (refreshState == REF_RUN) {
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// have not decremented outstandingEvents for refresh command
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// still check if there are no commands queued to force PD
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// entry after refresh completes
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return no_queued_cmds;
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} else {
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// ensure no commands in Q and no commands scheduled
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return (no_queued_cmds && (outstandingEvents == 0));
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}
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}
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void
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@ -1554,7 +1684,7 @@ DRAMCtrl::Rank::checkDrainDone()
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if (refreshState == REF_DRAIN) {
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DPRINTF(DRAM, "Refresh drain done, now precharging\n");
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refreshState = REF_PRE;
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refreshState = REF_PD_EXIT;
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// hand control back to the refresh event loop
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schedule(refreshEvent, curTick());
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@ -1602,26 +1732,59 @@ DRAMCtrl::Rank::processActivateEvent()
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void
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DRAMCtrl::Rank::processPrechargeEvent()
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{
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// counter should at least indicate one outstanding request
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// for this precharge
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assert(outstandingEvents > 0);
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// precharge complete, decrement count
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--outstandingEvents;
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// if we reached zero, then special conditions apply as we track
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// if all banks are precharged for the power models
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if (numBanksActive == 0) {
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// we should transition to the idle state when the last bank
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// is precharged
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schedulePowerEvent(PWR_IDLE, curTick());
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// no reads to this rank in the Q and no pending
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// RD/WR or refresh commands
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if (lowPowerEntryReady()) {
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// should still be in ACT state since bank still open
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assert(pwrState == PWR_ACT);
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// All banks closed - switch to precharge power down state.
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DPRINTF(DRAMState, "Rank %d sleep at tick %d\n",
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rank, curTick());
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powerDownSleep(PWR_PRE_PDN, curTick());
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} else {
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// we should transition to the idle state when the last bank
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// is precharged
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schedulePowerEvent(PWR_IDLE, curTick());
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}
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}
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}
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void
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DRAMCtrl::Rank::processWriteDoneEvent()
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{
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// counter should at least indicate one outstanding request
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// for this write
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assert(outstandingEvents > 0);
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// Write transfer on bus has completed
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// decrement per rank counter
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--outstandingEvents;
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}
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void
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DRAMCtrl::Rank::processRefreshEvent()
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{
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// when first preparing the refresh, remember when it was due
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if (refreshState == REF_IDLE) {
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if ((refreshState == REF_IDLE) || (refreshState == REF_SREF_EXIT)) {
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// remember when the refresh is due
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refreshDueAt = curTick();
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// proceed to drain
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refreshState = REF_DRAIN;
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// make nonzero while refresh is pending to ensure
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// power down and self-refresh are not entered
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++outstandingEvents;
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DPRINTF(DRAM, "Refresh due\n");
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}
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@ -1637,6 +1800,20 @@ DRAMCtrl::Rank::processRefreshEvent()
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// evaluated next
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DPRINTF(DRAM, "Refresh awaiting draining\n");
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return;
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} else {
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refreshState = REF_PD_EXIT;
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}
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}
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// at this point, ensure that rank is not in a power-down state
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if (refreshState == REF_PD_EXIT) {
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// if rank was sleeping and we have't started exit process,
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// wake-up for refresh
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if (inLowPowerState) {
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DPRINTF(DRAM, "Wake Up for refresh\n");
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// save state and return after refresh completes
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scheduleWakeUpEvent(memory.tXP);
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return;
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} else {
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refreshState = REF_PRE;
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@ -1645,9 +1822,8 @@ DRAMCtrl::Rank::processRefreshEvent()
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// at this point, ensure that all banks are precharged
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if (refreshState == REF_PRE) {
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// precharge any active bank if we are not already in the idle
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// state
|
||||
if (pwrState != PWR_IDLE) {
|
||||
// precharge any active bank
|
||||
if (numBanksActive != 0) {
|
||||
// at the moment, we use a precharge all even if there is
|
||||
// only a single bank open
|
||||
DPRINTF(DRAM, "Precharging all\n");
|
||||
|
|
@ -1681,15 +1857,22 @@ DRAMCtrl::Rank::processRefreshEvent()
|
|||
DPRINTF(DRAMPower, "%llu,PREA,0,%d\n",
|
||||
divCeil(pre_at, memory.tCK) -
|
||||
memory.timeStampOffset, rank);
|
||||
} else {
|
||||
} else if ((pwrState == PWR_IDLE) && (outstandingEvents == 1)) {
|
||||
// Banks are closed, have transitioned to IDLE state, and
|
||||
// no outstanding ACT,RD/WR,Auto-PRE sequence scheduled
|
||||
DPRINTF(DRAM, "All banks already precharged, starting refresh\n");
|
||||
|
||||
// go ahead and kick the power state machine into gear if
|
||||
// go ahead and kick the power state machine into gear since
|
||||
// we are already idle
|
||||
schedulePowerEvent(PWR_REF, curTick());
|
||||
} else {
|
||||
// banks state is closed but haven't transitioned pwrState to IDLE
|
||||
// or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled
|
||||
// should have outstanding precharge event in this case
|
||||
assert(prechargeEvent.scheduled());
|
||||
// will start refresh when pwrState transitions to IDLE
|
||||
}
|
||||
|
||||
refreshState = REF_RUN;
|
||||
assert(numBanksActive == 0);
|
||||
|
||||
// wait for all banks to be precharged, at which point the
|
||||
|
|
@ -1700,7 +1883,7 @@ DRAMCtrl::Rank::processRefreshEvent()
|
|||
}
|
||||
|
||||
// last but not least we perform the actual refresh
|
||||
if (refreshState == REF_RUN) {
|
||||
if (refreshState == REF_START) {
|
||||
// should never get here with any banks active
|
||||
assert(numBanksActive == 0);
|
||||
assert(pwrState == PWR_REF);
|
||||
|
|
@ -1720,25 +1903,70 @@ DRAMCtrl::Rank::processRefreshEvent()
|
|||
DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) -
|
||||
memory.timeStampOffset, rank);
|
||||
|
||||
// Update for next refresh
|
||||
refreshDueAt += memory.tREFI;
|
||||
|
||||
// make sure we did not wait so long that we cannot make up
|
||||
// for it
|
||||
if (refreshDueAt + memory.tREFI < ref_done_at) {
|
||||
if (refreshDueAt < ref_done_at) {
|
||||
fatal("Refresh was delayed so long we cannot catch up\n");
|
||||
}
|
||||
|
||||
// compensate for the delay in actually performing the refresh
|
||||
// when scheduling the next one
|
||||
schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP);
|
||||
// Run the refresh and schedule event to transition power states
|
||||
// when refresh completes
|
||||
refreshState = REF_RUN;
|
||||
schedule(refreshEvent, ref_done_at);
|
||||
return;
|
||||
}
|
||||
|
||||
if (refreshState == REF_RUN) {
|
||||
// should never get here with any banks active
|
||||
assert(numBanksActive == 0);
|
||||
assert(pwrState == PWR_REF);
|
||||
|
||||
assert(!powerEvent.scheduled());
|
||||
|
||||
// move to the idle power state once the refresh is done, this
|
||||
// will also move the refresh state machine to the refresh
|
||||
// idle state
|
||||
schedulePowerEvent(PWR_IDLE, ref_done_at);
|
||||
if ((memory.drainState() == DrainState::Draining) ||
|
||||
(memory.drainState() == DrainState::Drained)) {
|
||||
// if draining, do not re-enter low-power mode.
|
||||
// simply go to IDLE and wait
|
||||
schedulePowerEvent(PWR_IDLE, curTick());
|
||||
} else {
|
||||
// At the moment, we sleep when the refresh ends and wait to be
|
||||
// woken up again if previously in a low-power state.
|
||||
if (pwrStatePostRefresh != PWR_IDLE) {
|
||||
// power State should be power Refresh
|
||||
assert(pwrState == PWR_REF);
|
||||
DPRINTF(DRAMState, "Rank %d sleeping after refresh and was in "
|
||||
"power state %d before refreshing\n", rank,
|
||||
pwrStatePostRefresh);
|
||||
powerDownSleep(pwrState, curTick());
|
||||
|
||||
DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n",
|
||||
ref_done_at, refreshDueAt + memory.tREFI);
|
||||
// Force PRE power-down if there are no outstanding commands
|
||||
// in Q after refresh.
|
||||
} else if (lowPowerEntryReady()) {
|
||||
DPRINTF(DRAMState, "Rank %d sleeping after refresh but was NOT"
|
||||
" in a low power state before refreshing\n", rank);
|
||||
powerDownSleep(PWR_PRE_PDN, curTick());
|
||||
|
||||
} else {
|
||||
// move to the idle power state once the refresh is done, this
|
||||
// will also move the refresh state machine to the refresh
|
||||
// idle state
|
||||
schedulePowerEvent(PWR_IDLE, curTick());
|
||||
}
|
||||
}
|
||||
|
||||
// if transitioning to self refresh do not schedule a new refresh;
|
||||
// when waking from self refresh, a refresh is scheduled again.
|
||||
if (pwrStateTrans != PWR_SREF) {
|
||||
// compensate for the delay in actually performing the refresh
|
||||
// when scheduling the next one
|
||||
schedule(refreshEvent, refreshDueAt - memory.tRP);
|
||||
|
||||
DPRINTF(DRAMState, "Refresh done at %llu and next refresh"
|
||||
" at %llu\n", curTick(), refreshDueAt);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1763,9 +1991,133 @@ DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick)
|
|||
}
|
||||
}
|
||||
|
||||
void
|
||||
DRAMCtrl::Rank::powerDownSleep(PowerState pwr_state, Tick tick)
|
||||
{
|
||||
// if low power state is active low, schedule to active low power state.
|
||||
// in reality tCKE is needed to enter active low power. This is neglected
|
||||
// here and could be added in the future.
|
||||
if (pwr_state == PWR_ACT_PDN) {
|
||||
schedulePowerEvent(pwr_state, tick);
|
||||
// push command to DRAMPower
|
||||
cmdList.push_back(Command(MemCommand::PDN_F_ACT, 0, tick));
|
||||
DPRINTF(DRAMPower, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick,
|
||||
memory.tCK) - memory.timeStampOffset, rank);
|
||||
} else if (pwr_state == PWR_PRE_PDN) {
|
||||
// if low power state is precharge low, schedule to precharge low
|
||||
// power state. In reality tCKE is needed to enter active low power.
|
||||
// This is neglected here.
|
||||
schedulePowerEvent(pwr_state, tick);
|
||||
//push Command to DRAMPower
|
||||
cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick));
|
||||
DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick,
|
||||
memory.tCK) - memory.timeStampOffset, rank);
|
||||
} else if (pwr_state == PWR_REF) {
|
||||
// if a refresh just occured
|
||||
// transition to PRE_PDN now that all banks are closed
|
||||
// do not transition to SREF if commands are in Q; stay in PRE_PDN
|
||||
if (pwrStatePostRefresh == PWR_ACT_PDN || !lowPowerEntryReady()) {
|
||||
// prechage power down requires tCKE to enter. For simplicity
|
||||
// this is not considered.
|
||||
schedulePowerEvent(PWR_PRE_PDN, tick);
|
||||
//push Command to DRAMPower
|
||||
cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick));
|
||||
DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick,
|
||||
memory.tCK) - memory.timeStampOffset, rank);
|
||||
} else {
|
||||
// last low power State was power precharge
|
||||
assert(pwrStatePostRefresh == PWR_PRE_PDN);
|
||||
// self refresh requires time tCKESR to enter. For simplicity,
|
||||
// this is not considered.
|
||||
schedulePowerEvent(PWR_SREF, tick);
|
||||
// push Command to DRAMPower
|
||||
cmdList.push_back(Command(MemCommand::SREN, 0, tick));
|
||||
DPRINTF(DRAMPower, "%llu,SREN,0,%d\n", divCeil(tick,
|
||||
memory.tCK) - memory.timeStampOffset, rank);
|
||||
}
|
||||
}
|
||||
// Ensure that we don't power-down and back up in same tick
|
||||
// Once we commit to PD entry, do it and wait for at least 1tCK
|
||||
// This could be replaced with tCKE if/when that is added to the model
|
||||
wakeUpAllowedAt = tick + memory.tCK;
|
||||
|
||||
// Transitioning to a low power state, set flag
|
||||
inLowPowerState = true;
|
||||
}
|
||||
|
||||
void
|
||||
DRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay)
|
||||
{
|
||||
Tick wake_up_tick = std::max(curTick(), wakeUpAllowedAt);
|
||||
|
||||
DPRINTF(DRAMState, "Scheduling wake-up for rank %d at tick %d\n",
|
||||
rank, wake_up_tick);
|
||||
|
||||
// if waking for refresh, hold previous state
|
||||
// else reset state back to IDLE
|
||||
if (refreshState == REF_PD_EXIT) {
|
||||
pwrStatePostRefresh = pwrState;
|
||||
} else {
|
||||
// don't automatically transition back to LP state after next REF
|
||||
pwrStatePostRefresh = PWR_IDLE;
|
||||
}
|
||||
|
||||
// schedule wake-up with event to ensure entry has completed before
|
||||
// we try to wake-up
|
||||
schedule(wakeUpEvent, wake_up_tick);
|
||||
|
||||
for (auto &b : banks) {
|
||||
// respect both causality and any existing bank
|
||||
// constraints, some banks could already have a
|
||||
// (auto) precharge scheduled
|
||||
b.colAllowedAt = std::max(wake_up_tick + exit_delay, b.colAllowedAt);
|
||||
b.preAllowedAt = std::max(wake_up_tick + exit_delay, b.preAllowedAt);
|
||||
b.actAllowedAt = std::max(wake_up_tick + exit_delay, b.actAllowedAt);
|
||||
}
|
||||
// Transitioning out of low power state, clear flag
|
||||
inLowPowerState = false;
|
||||
|
||||
// push to DRAMPower
|
||||
// use pwrStateTrans for cases where we have a power event scheduled
|
||||
// to enter low power that has not yet been processed
|
||||
if (pwrStateTrans == PWR_ACT_PDN) {
|
||||
cmdList.push_back(Command(MemCommand::PUP_ACT, 0, wake_up_tick));
|
||||
DPRINTF(DRAMPower, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick,
|
||||
memory.tCK) - memory.timeStampOffset, rank);
|
||||
|
||||
} else if (pwrStateTrans == PWR_PRE_PDN) {
|
||||
cmdList.push_back(Command(MemCommand::PUP_PRE, 0, wake_up_tick));
|
||||
DPRINTF(DRAMPower, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick,
|
||||
memory.tCK) - memory.timeStampOffset, rank);
|
||||
} else if (pwrStateTrans == PWR_SREF) {
|
||||
cmdList.push_back(Command(MemCommand::SREX, 0, wake_up_tick));
|
||||
DPRINTF(DRAMPower, "%llu,SREX,0,%d\n", divCeil(wake_up_tick,
|
||||
memory.tCK) - memory.timeStampOffset, rank);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
DRAMCtrl::Rank::processWakeUpEvent()
|
||||
{
|
||||
// Should be in a power-down or self-refresh state
|
||||
assert((pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) ||
|
||||
(pwrState == PWR_SREF));
|
||||
|
||||
// Check current state to determine transition state
|
||||
if (pwrState == PWR_ACT_PDN) {
|
||||
// banks still open, transition to PWR_ACT
|
||||
schedulePowerEvent(PWR_ACT, curTick());
|
||||
} else {
|
||||
// transitioning from a precharge power-down or self-refresh state
|
||||
// banks are closed - transition to PWR_IDLE
|
||||
schedulePowerEvent(PWR_IDLE, curTick());
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
DRAMCtrl::Rank::processPowerEvent()
|
||||
{
|
||||
assert(curTick() >= pwrStateTick);
|
||||
// remember where we were, and for how long
|
||||
Tick duration = curTick() - pwrStateTick;
|
||||
PowerState prev_state = pwrState;
|
||||
|
|
@ -1773,36 +2125,80 @@ DRAMCtrl::Rank::processPowerEvent()
|
|||
// update the accounting
|
||||
pwrStateTime[prev_state] += duration;
|
||||
|
||||
// track to total idle time
|
||||
if ((prev_state == PWR_PRE_PDN) || (prev_state == PWR_ACT_PDN) ||
|
||||
(prev_state == PWR_SREF)) {
|
||||
totalIdleTime += duration;
|
||||
}
|
||||
|
||||
pwrState = pwrStateTrans;
|
||||
pwrStateTick = curTick();
|
||||
|
||||
if (pwrState == PWR_IDLE) {
|
||||
DPRINTF(DRAMState, "All banks precharged\n");
|
||||
// if rank was refreshing, make sure to start scheduling requests again
|
||||
if (prev_state == PWR_REF) {
|
||||
// bus IDLED prior to REF
|
||||
// counter should be one for refresh command only
|
||||
assert(outstandingEvents == 1);
|
||||
// REF complete, decrement count
|
||||
--outstandingEvents;
|
||||
|
||||
// if we were refreshing, make sure we start scheduling requests again
|
||||
if (prev_state == PWR_REF) {
|
||||
DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration);
|
||||
assert(pwrState == PWR_IDLE);
|
||||
|
||||
// kick things into action again
|
||||
refreshState = REF_IDLE;
|
||||
// a request event could be already scheduled by the state
|
||||
// machine of the other rank
|
||||
if (!memory.nextReqEvent.scheduled())
|
||||
schedule(memory.nextReqEvent, curTick());
|
||||
} else {
|
||||
assert(prev_state == PWR_ACT);
|
||||
|
||||
// if we have a pending refresh, and are now moving to
|
||||
// the idle state, direclty transition to a refresh
|
||||
if (refreshState == REF_RUN) {
|
||||
// there should be nothing waiting at this point
|
||||
assert(!powerEvent.scheduled());
|
||||
|
||||
// update the state in zero time and proceed below
|
||||
pwrState = PWR_REF;
|
||||
}
|
||||
DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration);
|
||||
// if sleeping after refresh
|
||||
if (pwrState != PWR_IDLE) {
|
||||
assert((pwrState == PWR_PRE_PDN) || (pwrState == PWR_SREF));
|
||||
DPRINTF(DRAMState, "Switching to power down state after refreshing"
|
||||
" rank %d at %llu tick\n", rank, curTick());
|
||||
}
|
||||
if (pwrState != PWR_SREF) {
|
||||
// rank is not available in SREF
|
||||
// don't transition to IDLE in this case
|
||||
refreshState = REF_IDLE;
|
||||
}
|
||||
// a request event could be already scheduled by the state
|
||||
// machine of the other rank
|
||||
if (!memory.nextReqEvent.scheduled()) {
|
||||
DPRINTF(DRAM, "Scheduling next request after refreshing rank %d\n",
|
||||
rank);
|
||||
schedule(memory.nextReqEvent, curTick());
|
||||
}
|
||||
} else if (pwrState == PWR_ACT) {
|
||||
if (refreshState == REF_PD_EXIT) {
|
||||
// kick the refresh event loop into action again
|
||||
assert(prev_state == PWR_ACT_PDN);
|
||||
|
||||
// go back to REF event and close banks
|
||||
refreshState = REF_PRE;
|
||||
schedule(refreshEvent, curTick());
|
||||
}
|
||||
} else if (pwrState == PWR_IDLE) {
|
||||
DPRINTF(DRAMState, "All banks precharged\n");
|
||||
if (prev_state == PWR_SREF) {
|
||||
// set refresh state to REF_SREF_EXIT, ensuring isAvailable
|
||||
// continues to return false during tXS after SREF exit
|
||||
// Schedule a refresh which kicks things back into action
|
||||
// when it finishes
|
||||
refreshState = REF_SREF_EXIT;
|
||||
schedule(refreshEvent, curTick() + memory.tXS);
|
||||
} else {
|
||||
// if we have a pending refresh, and are now moving to
|
||||
// the idle state, directly transition to a refresh
|
||||
if ((refreshState == REF_PRE) || (refreshState == REF_PD_EXIT)) {
|
||||
// ensure refresh is restarted only after final PRE command.
|
||||
// do not restart refresh if controller is in an intermediate
|
||||
// state, after PRE_PDN exit, when banks are IDLE but an
|
||||
// ACT is scheduled.
|
||||
if (!activateEvent.scheduled()) {
|
||||
// there should be nothing waiting at this point
|
||||
assert(!powerEvent.scheduled());
|
||||
// update the state in zero time and proceed below
|
||||
pwrState = PWR_REF;
|
||||
} else {
|
||||
// must have PRE scheduled to transition back to IDLE
|
||||
// and re-kick off refresh
|
||||
assert(prechargeEvent.scheduled());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// we transition to the refresh state, let the refresh state
|
||||
|
|
@ -1810,12 +2206,20 @@ DRAMCtrl::Rank::processPowerEvent()
|
|||
// scheduling of the next power state transition as well as the
|
||||
// following refresh
|
||||
if (pwrState == PWR_REF) {
|
||||
assert(refreshState == REF_PRE || refreshState == REF_PD_EXIT);
|
||||
DPRINTF(DRAMState, "Refreshing\n");
|
||||
|
||||
// kick the refresh event loop into action again, and that
|
||||
// in turn will schedule a transition to the idle power
|
||||
// state once the refresh is done
|
||||
assert(refreshState == REF_RUN);
|
||||
processRefreshEvent();
|
||||
if (refreshState == REF_PD_EXIT) {
|
||||
// Wait for PD exit timing to complete before issuing REF
|
||||
schedule(refreshEvent, curTick() + memory.tXP);
|
||||
} else {
|
||||
schedule(refreshEvent, curTick());
|
||||
}
|
||||
// Banks transitioned to IDLE, start REF
|
||||
refreshState = REF_START;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1852,6 +2256,9 @@ DRAMCtrl::Rank::updatePowerStats()
|
|||
refreshEnergy = energy.ref_energy * memory.devicesPerRank;
|
||||
actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank;
|
||||
preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank;
|
||||
actPowerDownEnergy = energy.f_act_pd_energy * memory.devicesPerRank;
|
||||
prePowerDownEnergy = energy.f_pre_pd_energy * memory.devicesPerRank;
|
||||
selfRefreshEnergy = energy.sref_energy * memory.devicesPerRank;
|
||||
totalEnergy = energy.total_energy * memory.devicesPerRank;
|
||||
averagePower = rank_power.average_power * memory.devicesPerRank;
|
||||
}
|
||||
|
|
@ -1880,14 +2287,15 @@ DRAMCtrl::Rank::regStats()
|
|||
using namespace Stats;
|
||||
|
||||
pwrStateTime
|
||||
.init(5)
|
||||
.init(6)
|
||||
.name(name() + ".memoryStateTime")
|
||||
.desc("Time in different power states");
|
||||
pwrStateTime.subname(0, "IDLE");
|
||||
pwrStateTime.subname(1, "REF");
|
||||
pwrStateTime.subname(2, "PRE_PDN");
|
||||
pwrStateTime.subname(3, "ACT");
|
||||
pwrStateTime.subname(4, "ACT_PDN");
|
||||
pwrStateTime.subname(2, "SREF");
|
||||
pwrStateTime.subname(3, "PRE_PDN");
|
||||
pwrStateTime.subname(4, "ACT");
|
||||
pwrStateTime.subname(5, "ACT_PDN");
|
||||
|
||||
actEnergy
|
||||
.name(name() + ".actEnergy")
|
||||
|
|
@ -1917,6 +2325,18 @@ DRAMCtrl::Rank::regStats()
|
|||
.name(name() + ".preBackEnergy")
|
||||
.desc("Energy for precharge background per rank (pJ)");
|
||||
|
||||
actPowerDownEnergy
|
||||
.name(name() + ".actPowerDownEnergy")
|
||||
.desc("Energy for active power-down per rank (pJ)");
|
||||
|
||||
prePowerDownEnergy
|
||||
.name(name() + ".prePowerDownEnergy")
|
||||
.desc("Energy for precharge power-down per rank (pJ)");
|
||||
|
||||
selfRefreshEnergy
|
||||
.name(name() + ".selfRefreshEnergy")
|
||||
.desc("Energy for self refresh per rank (pJ)");
|
||||
|
||||
totalEnergy
|
||||
.name(name() + ".totalEnergy")
|
||||
.desc("Total energy per rank (pJ)");
|
||||
|
|
@ -1925,6 +2345,10 @@ DRAMCtrl::Rank::regStats()
|
|||
.name(name() + ".averagePower")
|
||||
.desc("Core power per rank (mW)");
|
||||
|
||||
totalIdleTime
|
||||
.name(name() + ".totalIdleTime")
|
||||
.desc("Total Idle time Per DRAM Rank");
|
||||
|
||||
registerDumpCallback(new RankDumpCallback(this));
|
||||
}
|
||||
void
|
||||
|
|
@ -2215,11 +2639,22 @@ DRAMCtrl::drain()
|
|||
" resp: %d\n", writeQueue.size(), readQueue.size(),
|
||||
respQueue.size());
|
||||
|
||||
// the only part that is not drained automatically over time
|
||||
// the only queue that is not drained automatically over time
|
||||
// is the write queue, thus kick things into action if needed
|
||||
if (!writeQueue.empty() && !nextReqEvent.scheduled()) {
|
||||
schedule(nextReqEvent, curTick());
|
||||
}
|
||||
|
||||
// also need to kick off events to exit self-refresh
|
||||
for (auto r : ranks) {
|
||||
// force self-refresh exit, which in turn will issue auto-refresh
|
||||
if (r->pwrState == PWR_SREF) {
|
||||
DPRINTF(DRAM,"Rank%d: Forcing self-refresh wakeup in drain\n",
|
||||
r->rank);
|
||||
r->scheduleWakeUpEvent(tXS);
|
||||
}
|
||||
}
|
||||
|
||||
return DrainState::Draining;
|
||||
} else {
|
||||
return DrainState::Drained;
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@
|
|||
* Neha Agarwal
|
||||
* Omar Naji
|
||||
* Matthias Jung
|
||||
* Wendy Elsasser
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -87,6 +88,10 @@
|
|||
* controllers for future system architecture exploration",
|
||||
* Proc. ISPASS, 2014. If you use this model as part of your research
|
||||
* please cite the paper.
|
||||
*
|
||||
* The low-power functionality implements a staggered powerdown
|
||||
* similar to that described in "Optimized Active and Power-Down Mode
|
||||
* Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
|
||||
*/
|
||||
class DRAMCtrl : public AbstractMemory
|
||||
{
|
||||
|
|
@ -140,13 +145,14 @@ class DRAMCtrl : public AbstractMemory
|
|||
*/
|
||||
enum BusState {
|
||||
READ = 0,
|
||||
READ_TO_WRITE,
|
||||
WRITE,
|
||||
WRITE_TO_READ
|
||||
};
|
||||
|
||||
BusState busState;
|
||||
|
||||
/* bus state for next request event triggered */
|
||||
BusState busStateNext;
|
||||
|
||||
/**
|
||||
* Simple structure to hold the values needed to keep track of
|
||||
* commands for DRAMPower
|
||||
|
|
@ -197,6 +203,82 @@ class DRAMCtrl : public AbstractMemory
|
|||
};
|
||||
|
||||
|
||||
/**
|
||||
* The power state captures the different operational states of
|
||||
* the DRAM and interacts with the bus read/write state machine,
|
||||
* and the refresh state machine.
|
||||
*
|
||||
* PWR_IDLE : The idle state in which all banks are closed
|
||||
* From here can transition to: PWR_REF, PWR_ACT,
|
||||
* PWR_PRE_PDN
|
||||
*
|
||||
* PWR_REF : Auto-refresh state. Will transition when refresh is
|
||||
* complete based on power state prior to PWR_REF
|
||||
* From here can transition to: PWR_IDLE, PWR_PRE_PDN,
|
||||
* PWR_SREF
|
||||
*
|
||||
* PWR_SREF : Self-refresh state. Entered after refresh if
|
||||
* previous state was PWR_PRE_PDN
|
||||
* From here can transition to: PWR_IDLE
|
||||
*
|
||||
* PWR_PRE_PDN : Precharge power down state
|
||||
* From here can transition to: PWR_REF, PWR_IDLE
|
||||
*
|
||||
* PWR_ACT : Activate state in which one or more banks are open
|
||||
* From here can transition to: PWR_IDLE, PWR_ACT_PDN
|
||||
*
|
||||
* PWR_ACT_PDN : Activate power down state
|
||||
* From here can transition to: PWR_ACT
|
||||
*/
|
||||
enum PowerState {
|
||||
PWR_IDLE = 0,
|
||||
PWR_REF,
|
||||
PWR_SREF,
|
||||
PWR_PRE_PDN,
|
||||
PWR_ACT,
|
||||
PWR_ACT_PDN
|
||||
};
|
||||
|
||||
/**
|
||||
* The refresh state is used to control the progress of the
|
||||
* refresh scheduling. When normal operation is in progress the
|
||||
* refresh state is idle. Once tREFI has elasped, a refresh event
|
||||
* is triggered to start the following STM transitions which are
|
||||
* used to issue a refresh and return back to normal operation
|
||||
*
|
||||
* REF_IDLE : IDLE state used during normal operation
|
||||
* From here can transition to: REF_DRAIN
|
||||
*
|
||||
* REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
|
||||
* after self-refresh exit completes
|
||||
* From here can transition to: REF_DRAIN
|
||||
*
|
||||
* REF_DRAIN : Drain state in which on going accesses complete.
|
||||
* From here can transition to: REF_PD_EXIT
|
||||
*
|
||||
* REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
|
||||
* Next state dependent on whether banks are open
|
||||
* From here can transition to: REF_PRE, REF_START
|
||||
*
|
||||
* REF_PRE : Close (precharge) all open banks
|
||||
* From here can transition to: REF_START
|
||||
*
|
||||
* REF_START : Issue refresh command and update DRAMPower stats
|
||||
* From here can transition to: REF_RUN
|
||||
*
|
||||
* REF_RUN : Refresh running, waiting for tRFC to expire
|
||||
* From here can transition to: REF_IDLE, REF_SREF_EXIT
|
||||
*/
|
||||
enum RefreshState {
|
||||
REF_IDLE = 0,
|
||||
REF_DRAIN,
|
||||
REF_PD_EXIT,
|
||||
REF_SREF_EXIT,
|
||||
REF_PRE,
|
||||
REF_START,
|
||||
REF_RUN
|
||||
};
|
||||
|
||||
/**
|
||||
* Rank class includes a vector of banks. Refresh and Power state
|
||||
* machines are defined per rank. Events required to change the
|
||||
|
|
@ -209,41 +291,6 @@ class DRAMCtrl : public AbstractMemory
|
|||
|
||||
private:
|
||||
|
||||
/**
|
||||
* The power state captures the different operational states of
|
||||
* the DRAM and interacts with the bus read/write state machine,
|
||||
* and the refresh state machine. In the idle state all banks are
|
||||
* precharged. From there we either go to an auto refresh (as
|
||||
* determined by the refresh state machine), or to a precharge
|
||||
* power down mode. From idle the memory can also go to the active
|
||||
* state (with one or more banks active), and in turn from there
|
||||
* to active power down. At the moment we do not capture the deep
|
||||
* power down and self-refresh state.
|
||||
*/
|
||||
enum PowerState {
|
||||
PWR_IDLE = 0,
|
||||
PWR_REF,
|
||||
PWR_PRE_PDN,
|
||||
PWR_ACT,
|
||||
PWR_ACT_PDN
|
||||
};
|
||||
|
||||
/**
|
||||
* The refresh state is used to control the progress of the
|
||||
* refresh scheduling. When normal operation is in progress the
|
||||
* refresh state is idle. From there, it progresses to the refresh
|
||||
* drain state once tREFI has passed. The refresh drain state
|
||||
* captures the DRAM row active state, as it will stay there until
|
||||
* all ongoing accesses complete. Thereafter all banks are
|
||||
* precharged, and lastly, the DRAM is refreshed.
|
||||
*/
|
||||
enum RefreshState {
|
||||
REF_IDLE = 0,
|
||||
REF_DRAIN,
|
||||
REF_PRE,
|
||||
REF_RUN
|
||||
};
|
||||
|
||||
/**
|
||||
* A reference to the parent DRAMCtrl instance
|
||||
*/
|
||||
|
|
@ -251,29 +298,20 @@ class DRAMCtrl : public AbstractMemory
|
|||
|
||||
/**
|
||||
* Since we are taking decisions out of order, we need to keep
|
||||
* track of what power transition is happening at what time, such
|
||||
* that we can go back in time and change history. For example, if
|
||||
* we precharge all banks and schedule going to the idle state, we
|
||||
* might at a later point decide to activate a bank before the
|
||||
* transition to idle would have taken place.
|
||||
* track of what power transition is happening at what time
|
||||
*/
|
||||
PowerState pwrStateTrans;
|
||||
|
||||
/**
|
||||
* Current power state.
|
||||
* Previous low-power state, which will be re-entered after refresh.
|
||||
*/
|
||||
PowerState pwrState;
|
||||
PowerState pwrStatePostRefresh;
|
||||
|
||||
/**
|
||||
* Track when we transitioned to the current power state
|
||||
*/
|
||||
Tick pwrStateTick;
|
||||
|
||||
/**
|
||||
* current refresh state
|
||||
*/
|
||||
RefreshState refreshState;
|
||||
|
||||
/**
|
||||
* Keep track of when a refresh is due.
|
||||
*/
|
||||
|
|
@ -298,9 +336,30 @@ class DRAMCtrl : public AbstractMemory
|
|||
*/
|
||||
Stats::Scalar preBackEnergy;
|
||||
|
||||
/*
|
||||
* Active Power-Down Energy
|
||||
*/
|
||||
Stats::Scalar actPowerDownEnergy;
|
||||
|
||||
/*
|
||||
* Precharge Power-Down Energy
|
||||
*/
|
||||
Stats::Scalar prePowerDownEnergy;
|
||||
|
||||
/*
|
||||
* self Refresh Energy
|
||||
*/
|
||||
Stats::Scalar selfRefreshEnergy;
|
||||
|
||||
Stats::Scalar totalEnergy;
|
||||
Stats::Scalar averagePower;
|
||||
|
||||
/**
|
||||
* Stat to track total DRAM idle time
|
||||
*
|
||||
*/
|
||||
Stats::Scalar totalIdleTime;
|
||||
|
||||
/**
|
||||
* Track time spent in each power state.
|
||||
*/
|
||||
|
|
@ -322,11 +381,48 @@ class DRAMCtrl : public AbstractMemory
|
|||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Current power state.
|
||||
*/
|
||||
PowerState pwrState;
|
||||
|
||||
/**
|
||||
* current refresh state
|
||||
*/
|
||||
RefreshState refreshState;
|
||||
|
||||
/**
|
||||
* rank is in or transitioning to power-down or self-refresh
|
||||
*/
|
||||
bool inLowPowerState;
|
||||
|
||||
/**
|
||||
* Current Rank index
|
||||
*/
|
||||
uint8_t rank;
|
||||
|
||||
/**
|
||||
* Track number of packets in read queue going to this rank
|
||||
*/
|
||||
uint32_t readEntries;
|
||||
|
||||
/**
|
||||
* Track number of packets in write queue going to this rank
|
||||
*/
|
||||
uint32_t writeEntries;
|
||||
|
||||
/**
|
||||
* Number of ACT, RD, and WR events currently scheduled
|
||||
* Incremented when a refresh event is started as well
|
||||
* Used to determine when a low-power state can be entered
|
||||
*/
|
||||
uint8_t outstandingEvents;
|
||||
|
||||
/**
|
||||
* delay power-down and self-refresh exit until this requirement is met
|
||||
*/
|
||||
Tick wakeUpAllowedAt;
|
||||
|
||||
/**
|
||||
* One DRAMPower instance per rank
|
||||
*/
|
||||
|
|
@ -377,6 +473,10 @@ class DRAMCtrl : public AbstractMemory
|
|||
|
||||
/**
|
||||
* Check if the current rank is available for scheduling.
|
||||
* Rank will be unavailable if refresh is ongoing.
|
||||
* This includes refresh events explicitly scheduled from the the
|
||||
* controller or memory initiated events which will occur during
|
||||
* self-refresh mode.
|
||||
*
|
||||
* @param Return true if the rank is idle from a refresh point of view
|
||||
*/
|
||||
|
|
@ -391,6 +491,29 @@ class DRAMCtrl : public AbstractMemory
|
|||
*/
|
||||
bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
|
||||
|
||||
/**
|
||||
* Trigger a self-refresh exit if there are entries enqueued
|
||||
* Exit if there are any read entries regardless of the bus state.
|
||||
* If we are currently issuing write commands, exit if we have any
|
||||
* write commands enqueued as well.
|
||||
* Could expand this in the future to analyze state of entire queue
|
||||
* if needed.
|
||||
*
|
||||
* @return boolean indicating self-refresh exit should be scheduled
|
||||
*/
|
||||
bool forceSelfRefreshExit() const {
|
||||
return (readEntries != 0) ||
|
||||
((memory.busStateNext == WRITE) && (writeEntries != 0));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the current rank is idle and should enter a low-pwer state
|
||||
*
|
||||
* @param Return true if the there are no read commands in Q
|
||||
* and there are no outstanding events
|
||||
*/
|
||||
bool lowPowerEntryReady() const;
|
||||
|
||||
/**
|
||||
* Let the rank check if it was waiting for requests to drain
|
||||
* to allow it to transition states.
|
||||
|
|
@ -415,6 +538,27 @@ class DRAMCtrl : public AbstractMemory
|
|||
*/
|
||||
void computeStats();
|
||||
|
||||
/**
|
||||
* Schedule a transition to power-down (sleep)
|
||||
*
|
||||
* @param pwr_state Power state to transition to
|
||||
* @param tick Absolute tick when transition should take place
|
||||
*/
|
||||
void powerDownSleep(PowerState pwr_state, Tick tick);
|
||||
|
||||
/**
|
||||
* schedule and event to wake-up from power-down or self-refresh
|
||||
* and update bank timing parameters
|
||||
*
|
||||
* @param exit_delay Relative tick defining the delay required between
|
||||
* low-power exit and the next command
|
||||
*/
|
||||
void scheduleWakeUpEvent(Tick exit_delay);
|
||||
|
||||
void processWriteDoneEvent();
|
||||
EventWrapper<Rank, &Rank::processWriteDoneEvent>
|
||||
writeDoneEvent;
|
||||
|
||||
void processActivateEvent();
|
||||
EventWrapper<Rank, &Rank::processActivateEvent>
|
||||
activateEvent;
|
||||
|
|
@ -431,6 +575,10 @@ class DRAMCtrl : public AbstractMemory
|
|||
EventWrapper<Rank, &Rank::processPowerEvent>
|
||||
powerEvent;
|
||||
|
||||
void processWakeUpEvent();
|
||||
EventWrapper<Rank, &Rank::processWakeUpEvent>
|
||||
wakeUpEvent;
|
||||
|
||||
};
|
||||
|
||||
// define the process to compute stats on simulation exit
|
||||
|
|
|
|||
Loading…
Reference in a new issue