Make syscalls flatten their register indices, and also call into the ISA's setSyscallReturn function rather than having a duplicated one.
--HG-- extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
This commit is contained in:
parent
156cf0db51
commit
1d7d7df315
1 changed files with 7 additions and 18 deletions
|
@ -285,35 +285,24 @@ template <class Impl>
|
||||||
TheISA::IntReg
|
TheISA::IntReg
|
||||||
SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
|
SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
|
||||||
{
|
{
|
||||||
return this->readArchIntReg(SparcISA::ArgumentReg0 + i, tid);
|
IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
|
||||||
|
SparcISA::ArgumentReg0 + i);
|
||||||
|
return this->readArchIntReg(idx, tid);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
SparcO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
|
SparcO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
|
||||||
{
|
{
|
||||||
this->setArchIntReg(SparcISA::ArgumentReg0 + i, val, tid);
|
IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
|
||||||
|
SparcISA::ArgumentReg0 + i);
|
||||||
|
this->setArchIntReg(idx, val, tid);
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
SparcO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
|
SparcO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
|
||||||
{
|
{
|
||||||
// check for error condition. SPARC syscall convention is to
|
TheISA::setSyscallReturn(return_value, this->tcBase(tid));
|
||||||
// indicate success/failure in reg the carry bit of the ccr
|
|
||||||
// and put the return value itself in the standard return value reg ().
|
|
||||||
if (return_value.successful()) {
|
|
||||||
// no error, clear XCC.C
|
|
||||||
this->setMiscReg(SparcISA::MISCREG_CCR,
|
|
||||||
this->readMiscReg(SparcISA::MISCREG_CCR, tid) & 0xEE, tid);
|
|
||||||
this->setArchIntReg(SparcISA::ReturnValueReg,
|
|
||||||
return_value.value(), tid);
|
|
||||||
} else {
|
|
||||||
// got an error, set XCC.C
|
|
||||||
this->setMiscReg(SparcISA::MISCREG_CCR,
|
|
||||||
this->readMiscReg(SparcISA::MISCREG_CCR, tid) | 0x11, tid);
|
|
||||||
this->setArchIntReg(SparcISA::ReturnValueReg,
|
|
||||||
return_value.value(), tid);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue