X86: Add a trace flag for tracing faults.
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@ -113,6 +113,7 @@ if env['TARGET_ISA'] == 'x86':
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TraceFlag('LocalApic', "Local APIC debugging")
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TraceFlag('LocalApic', "Local APIC debugging")
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TraceFlag('PageTableWalker', \
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TraceFlag('PageTableWalker', \
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"Page table walker state machine debugging")
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"Page table walker state machine debugging")
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TraceFlag('Faults', "Trace all faults/exceptions/traps")
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SimObject('X86LocalApic.py')
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SimObject('X86LocalApic.py')
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SimObject('X86System.py')
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SimObject('X86System.py')
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@ -103,6 +103,8 @@ namespace X86ISA
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void X86FaultBase::invoke(ThreadContext * tc)
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void X86FaultBase::invoke(ThreadContext * tc)
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{
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{
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Addr pc = tc->readPC();
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DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
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using namespace X86ISAInst::RomLabels;
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using namespace X86ISAInst::RomLabels;
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HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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MicroPC entry;
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MicroPC entry;
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@ -116,7 +118,7 @@ namespace X86ISA
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entry = extern_label_legacyModeInterrupt;
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entry = extern_label_legacyModeInterrupt;
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}
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}
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tc->setIntReg(INTREG_MICRO(1), vector);
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tc->setIntReg(INTREG_MICRO(1), vector);
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tc->setIntReg(INTREG_MICRO(7), tc->readPC());
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tc->setIntReg(INTREG_MICRO(7), pc);
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if (errorCode != (uint64_t)(-1)) {
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if (errorCode != (uint64_t)(-1)) {
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if (m5reg.mode == LongMode) {
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if (m5reg.mode == LongMode) {
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entry = extern_label_longModeInterruptWithError;
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entry = extern_label_longModeInterruptWithError;
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@ -133,6 +135,18 @@ namespace X86ISA
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tc->setNextMicroPC(romMicroPC(entry) + 1);
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tc->setNextMicroPC(romMicroPC(entry) + 1);
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}
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}
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std::string
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X86FaultBase::describe() const
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{
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std::stringstream ss;
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ccprintf(ss, "%s", mnemonic());
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if (errorCode != (uint64_t)(-1)) {
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ccprintf(ss, "(%#x)", errorCode);
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}
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return ss.str();
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}
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void X86Trap::invoke(ThreadContext * tc)
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void X86Trap::invoke(ThreadContext * tc)
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{
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{
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X86FaultBase::invoke(tc);
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X86FaultBase::invoke(tc);
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@ -163,6 +177,14 @@ namespace X86ISA
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}
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}
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}
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}
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std::string
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PageFault::describe() const
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{
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std::stringstream ss;
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ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
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return ss.str();
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}
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#endif
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#endif
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} // namespace X86ISA
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} // namespace X86ISA
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@ -62,6 +62,8 @@
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#include "base/misc.hh"
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#include "base/misc.hh"
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#include "sim/faults.hh"
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#include "sim/faults.hh"
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#include <string>
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namespace X86ISA
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namespace X86ISA
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{
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{
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// Base class for all x86 "faults" where faults is in the m5 sense
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// Base class for all x86 "faults" where faults is in the m5 sense
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@ -102,6 +104,8 @@ namespace X86ISA
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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void invoke(ThreadContext * tc);
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virtual std::string describe() const;
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#endif
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#endif
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};
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};
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@ -342,6 +346,8 @@ namespace X86ISA
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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void invoke(ThreadContext * tc);
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virtual std::string describe() const;
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#endif
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#endif
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};
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};
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@ -414,7 +420,7 @@ namespace X86ISA
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{
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{
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public:
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public:
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SoftwareInterrupt(uint8_t _vector) :
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SoftwareInterrupt(uint8_t _vector) :
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X86Interrupt("Software Interrupt", "INTn", _vector)
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X86Interrupt("Software Interrupt", "#INTR", _vector)
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{}
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{}
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bool isSoft()
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bool isSoft()
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