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alpha: Quick fix for things related to TLB MRU cache.

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simple-timing test for ALPHA_FS breaks.

--HG--
extra : convert_revision : 5a1b05cddd480849913da81a3b3931fec16485a8
This commit is contained in:
Vincentius Robby 2007-08-08 18:38:19 -04:00
parent 9493501fdb
commit 1caed14654
2 changed files with 14 additions and 11 deletions
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13
src/arch/alpha/tlb.cc
View file

@ -75,7 +75,7 @@ TLB::~TLB()
// look up an entry in the TLB
PTE *
TLB::lookup(Addr vpn, uint8_t asn) const
TLB::lookup(Addr vpn, uint8_t asn)
{
// assume not found...
PTE *retval = NULL;
@ -94,7 +94,7 @@ TLB::lookup(Addr vpn, uint8_t asn) const
}
}
if (retval == NULL)
if (retval == NULL) {
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
while (i->first == vpn) {
@ -102,10 +102,7 @@ TLB::lookup(Addr vpn, uint8_t asn) const
PTE *pte = &table[index];
assert(pte->valid);
if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
retval = pte;
PTECache[2] = PTECache[1];
PTECache[1] = PTECache[0];
PTECache[0] = pte;
retval = updateCache(pte);
break;
}
@ -315,7 +312,7 @@ ITB::regStats()
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc) const
ITB::translate(RequestPtr &req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if(FULL_SYSTEM && PcPAL(req->getPC()))
@ -477,7 +474,7 @@ DTB::regStats()
}
Fault
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
{
Addr pc = tc->readPC();

12
src/arch/alpha/tlb.hh
View file

@ -61,7 +61,7 @@ namespace AlphaISA
int nlu; // not last used entry (for replacement)
void nextnlu() { if (++nlu >= size) nlu = 0; }
PTE *lookup(Addr vpn, uint8_t asn) const;
PTE *lookup(Addr vpn, uint8_t asn);
public:
TLB(const std::string &name, int size);
@ -92,6 +92,12 @@ namespace AlphaISA
// Most recently used page table entries
PTE *PTECache[3];
inline void flushCache() { memset(PTECache, 0, 3 * sizeof(PTE*)); }
inline PTE* updateCache(PTE *pte) {
PTECache[2] = PTECache[1];
PTECache[1] = PTECache[0];
PTECache[0] = pte;
return pte;
}
};
class ITB : public TLB
@ -106,7 +112,7 @@ namespace AlphaISA
ITB(const std::string &name, int size);
virtual void regStats();
Fault translate(RequestPtr &req, ThreadContext *tc) const;
Fault translate(RequestPtr &req, ThreadContext *tc);
};
class DTB : public TLB
@ -129,7 +135,7 @@ namespace AlphaISA
DTB(const std::string &name, int size);
virtual void regStats();
Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
};
}