ARM: Fix custom writer/reader code for non indexed operands.
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4b87bc887a
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1c0d9806e5
1 changed files with 17 additions and 13 deletions
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@ -388,12 +388,14 @@ class Operand(object):
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type (e.g., "32-bit integer register").'''
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def buildReadCode(self, func = None):
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code = self.read_code % {"name": self.base_name,
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subst_dict = {"name": self.base_name,
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"func": func,
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"op_idx": self.src_reg_idx,
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"reg_idx": self.reg_spec,
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"size": self.size,
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"ctype": self.ctype}
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if hasattr(self, 'src_reg_idx'):
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subst_dict['op_idx'] = self.src_reg_idx
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code = self.read_code % subst_dict
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if self.size != self.dflt_size:
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return '%s = bits(%s, %d, 0);\n' % \
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(self.base_name, code, self.size-1)
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@ -406,13 +408,15 @@ class Operand(object):
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final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
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else:
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final_val = self.base_name
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code = self.write_code % {"name": self.base_name,
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subst_dict = {"name": self.base_name,
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"func": func,
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"op_idx": self.dest_reg_idx,
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"reg_idx": self.reg_spec,
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"size": self.size,
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"ctype": self.ctype,
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"final_val": final_val}
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if hasattr(self, 'dest_reg_idx'):
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subst_dict['op_idx'] = self.dest_reg_idx
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code = self.write_code % subst_dict
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return '''
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{
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%s final_val = %s;
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