arm: Support >2GB of memory for AArch64 systems
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16262a8fc3
commit
1c0ae90027
2 changed files with 24 additions and 12 deletions
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@ -246,19 +246,30 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None,
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if dtb_filename:
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self.dtb_filename = binary(dtb_filename)
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self.machine_type = machine_type
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if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
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print "The currently selected ARM platforms doesn't support"
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print " the amount of DRAM you've selected. Please try"
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print " another platform"
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sys.exit(1)
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# Ensure that writes to the UART actually go out early in the boot
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boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
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'lpj=19988480 norandmaps rw loglevel=8 ' + \
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'mem=%s root=/dev/sda1' % mdesc.mem()
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self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
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size = mdesc.mem())]
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self.mem_ranges = []
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size_remain = long(Addr(mdesc.mem()))
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for region in self.realview._mem_regions:
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if size_remain > long(region[1]):
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self.mem_ranges.append(AddrRange(region[0], size=region[1]))
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size_remain = size_remain - long(region[1])
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else:
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self.mem_ranges.append(AddrRange(region[0], size=size_remain))
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size_remain = 0
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break
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warn("Memory size specified spans more than one region. Creating" \
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" another memory controller for that range.")
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if size_remain > 0:
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fatal("The currently selected ARM platforms doesn't support" \
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" the amount of DRAM you've selected. Please try" \
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" another platform")
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self.realview.setupBootLoader(self.membus, self, binary)
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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@ -184,8 +184,7 @@ class RealView(Platform):
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pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
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pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
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" be compatible with the pci-generic-host or the legacy host bridge?")
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mem_start_addr = Param.Addr(0, "Start address of main memory")
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max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
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_mem_regions = [(Addr(0), Addr('256MB'))]
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def attachPciDevices(self):
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pass
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@ -444,8 +443,7 @@ class RealViewEB(RealView):
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self.smcreg_fake.clk_domain = clkdomain
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class VExpress_EMM(RealView):
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mem_start_addr = '2GB'
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max_mem_size = '2GB'
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_mem_regions = [(Addr('2GB'), Addr('2GB'))]
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pci_cfg_base = 0x30000000
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uart = Pl011(pio_addr=0x1c090000, int_num=37)
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realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
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@ -602,6 +600,9 @@ class VExpress_EMM(RealView):
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class VExpress_EMM64(VExpress_EMM):
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pci_io_base = 0x2f000000
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pci_cfg_gen_offsets = True
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# Three memory regions are specified totalling 512GB
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_mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
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(Addr('512GB'), Addr('480GB'))]
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
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self.nvmem.port = mem_bus.master
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