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arm: Support >2GB of memory for AArch64 systems

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This commit is contained in:
Ali Saidi 2014-09-03 07:43:05 -04:00
parent 16262a8fc3
commit 1c0ae90027
2 changed files with 24 additions and 12 deletions
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27
configs/common/FSConfig.py
View file

@ -246,19 +246,30 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None,
if dtb_filename: if dtb_filename:
self.dtb_filename = binary(dtb_filename) self.dtb_filename = binary(dtb_filename)
self.machine_type = machine_type self.machine_type = machine_type
if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
print "The currently selected ARM platforms doesn't support"
print " the amount of DRAM you've selected. Please try"
print " another platform"
sys.exit(1)
# Ensure that writes to the UART actually go out early in the boot # Ensure that writes to the UART actually go out early in the boot
boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
'lpj=19988480 norandmaps rw loglevel=8 ' + \ 'lpj=19988480 norandmaps rw loglevel=8 ' + \
'mem=%s root=/dev/sda1' % mdesc.mem() 'mem=%s root=/dev/sda1' % mdesc.mem()
self.mem_ranges = [AddrRange(self.realview.mem_start_addr, self.mem_ranges = []
size = mdesc.mem())] size_remain = long(Addr(mdesc.mem()))
for region in self.realview._mem_regions:
if size_remain > long(region[1]):
self.mem_ranges.append(AddrRange(region[0], size=region[1]))
size_remain = size_remain - long(region[1])
else:
self.mem_ranges.append(AddrRange(region[0], size=size_remain))
size_remain = 0
break
warn("Memory size specified spans more than one region. Creating" \
" another memory controller for that range.")
if size_remain > 0:
fatal("The currently selected ARM platforms doesn't support" \
" the amount of DRAM you've selected. Please try" \
" another platform")
self.realview.setupBootLoader(self.membus, self, binary) self.realview.setupBootLoader(self.membus, self, binary)
self.gic_cpu_addr = self.realview.gic.cpu_addr self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30 self.flags_addr = self.realview.realview_io.pio_addr + 0x30

9
src/dev/arm/RealView.py
View file

@ -184,8 +184,7 @@ class RealView(Platform):
pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
" be compatible with the pci-generic-host or the legacy host bridge?") " be compatible with the pci-generic-host or the legacy host bridge?")
mem_start_addr = Param.Addr(0, "Start address of main memory") _mem_regions = [(Addr(0), Addr('256MB'))]
max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
def attachPciDevices(self): def attachPciDevices(self):
pass pass
@ -444,8 +443,7 @@ class RealViewEB(RealView):
self.smcreg_fake.clk_domain = clkdomain self.smcreg_fake.clk_domain = clkdomain
class VExpress_EMM(RealView): class VExpress_EMM(RealView):
mem_start_addr = '2GB' _mem_regions = [(Addr('2GB'), Addr('2GB'))]
max_mem_size = '2GB'
pci_cfg_base = 0x30000000 pci_cfg_base = 0x30000000
uart = Pl011(pio_addr=0x1c090000, int_num=37) uart = Pl011(pio_addr=0x1c090000, int_num=37)
realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
@ -602,6 +600,9 @@ class VExpress_EMM(RealView):
class VExpress_EMM64(VExpress_EMM): class VExpress_EMM64(VExpress_EMM):
pci_io_base = 0x2f000000 pci_io_base = 0x2f000000
pci_cfg_gen_offsets = True pci_cfg_gen_offsets = True
# Three memory regions are specified totalling 512GB
_mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
(Addr('512GB'), Addr('480GB'))]
def setupBootLoader(self, mem_bus, cur_sys, loc): def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
self.nvmem.port = mem_bus.master self.nvmem.port = mem_bus.master