misc: Bugfix in TLM memInhibit Command
memInhibitAsserted() has been removed from packet.hh. This change has been reflected in TLM based SystemC memory. This patch also adds a number of panics asserting the SystemC memory only sees requests it expects. Committed by Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
parent
90cb9827be
commit
1b46c175fc
1 changed files with 14 additions and 5 deletions
|
@ -91,6 +91,13 @@ sc_transactor::recvAtomic(PacketPtr packet)
|
|||
CAUGHT_UP;
|
||||
SC_REPORT_INFO("transactor", "recvAtomic hasn't been tested much");
|
||||
|
||||
panic_if(packet->cacheResponding(), "Should not see packets where cache "
|
||||
"is responding");
|
||||
|
||||
panic_if(!(packet->isRead() || packet->isWrite()),
|
||||
"Should only see read and writes at TLM memory\n");
|
||||
|
||||
|
||||
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
|
||||
|
||||
|
||||
|
@ -172,15 +179,17 @@ sc_transactor::recvTimingReq(PacketPtr packet)
|
|||
{
|
||||
CAUGHT_UP;
|
||||
|
||||
panic_if(packet->cacheResponding(), "Should not see packets where cache "
|
||||
"is responding");
|
||||
|
||||
panic_if(!(packet->isRead() || packet->isWrite()),
|
||||
"Should only see read and writes at TLM memory\n");
|
||||
|
||||
|
||||
/* We should never get a second request after noting that a retry is
|
||||
* required */
|
||||
sc_assert(!needToSendRequestRetry);
|
||||
|
||||
// simply drop inhibited packets and clean evictions
|
||||
if (packet->memInhibitAsserted() ||
|
||||
packet->cmd == MemCmd::CleanEvict)
|
||||
return true;
|
||||
|
||||
/* Remember if a request comes in while we're blocked so that a retry
|
||||
* can be sent to gem5 */
|
||||
if (blockingRequest) {
|
||||
|
|
Loading…
Reference in a new issue