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This commit is contained in:
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4 changed files with 133 additions and 93 deletions
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@ -45,39 +45,49 @@
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using namespace std;
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std::string MiscRegFile::miscRegNames[NumMiscRegs] =
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{"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
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"Random", "VPEControl", "VPEConf0", "VPEConf1", "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
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"EntryLo0", "TCStatus", "TCBind", "TCRestart", "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
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"EntryLo1", "", "", "", "", "", "", "",
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"Context", "ContextConfig", "", "", "", "", "", "",
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"PageMask", "PageGrain", "", "", "", "", "", "",
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"Wired", "SRSConf0", "SRCConf1", "SRSConf2", "SRSConf3", "SRSConf4", "", "",
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"HWREna", "", "", "", "", "", "", "",
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"BadVAddr", "", "", "", "", "", "", "",
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"Count", "", "", "", "", "", "", "",
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"EntryHi", "", "", "", "", "", "", "",
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"Compare", "", "", "", "", "", "", "",
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"Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
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"Cause", "", "", "", "", "", "", "",
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"EPC", "", "", "", "", "", "", "",
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"PRId", "EBase", "", "", "", "", "", "",
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"Config", "Config1", "Config2", "Config3", "", "", "", "",
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"LLAddr", "", "", "", "", "", "", "",
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"WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
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"WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
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"XCContext64", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"Debug", "TraceControl1", "TraceControl2", "UserTraceData", "TraceBPC", "", "", "",
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"DEPC", "", "", "", "", "", "", "",
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"PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
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"ErrCtl", "", "", "", "", "", "", "",
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"CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
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"TagLo0", "DataLo1", "TagLo2", "DataLo3", "TagLo4", "DataLo5", "TagLo6", "DataLo7",
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"TagHi0", "DataHi1", "TagHi2", "DataHi3", "TagHi4", "DataHi5", "TagHi6", "DataHi7",
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"ErrorEPC", "", "", "", "", "", "", "",
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"DESAVE", "", "", "", "", "", "", "",
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"LLFlag"
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{
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"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
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"Random", "VPEControl", "VPEConf0", "VPEConf1",
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"YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
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"EntryLo0", "TCStatus", "TCBind", "TCRestart",
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"TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
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"EntryLo1", "", "", "", "", "", "", "",
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"Context", "ContextConfig", "", "", "", "", "", "",
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"PageMask", "PageGrain", "", "", "", "", "", "",
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"Wired", "SRSConf0", "SRCConf1", "SRSConf2",
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"SRSConf3", "SRSConf4", "", "",
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"HWREna", "", "", "", "", "", "", "",
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"BadVAddr", "", "", "", "", "", "", "",
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"Count", "", "", "", "", "", "", "",
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"EntryHi", "", "", "", "", "", "", "",
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"Compare", "", "", "", "", "", "", "",
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"Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
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"Cause", "", "", "", "", "", "", "",
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"EPC", "", "", "", "", "", "", "",
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"PRId", "EBase", "", "", "", "", "", "",
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"Config", "Config1", "Config2", "Config3", "", "", "", "",
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"LLAddr", "", "", "", "", "", "", "",
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"WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
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"WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
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"WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
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"WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
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"XCContext64", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"Debug", "TraceControl1", "TraceControl2", "UserTraceData",
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"TraceBPC", "", "", "",
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"DEPC", "", "", "", "", "", "", "",
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"PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
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"PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
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"ErrCtl", "", "", "", "", "", "", "",
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"CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
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"TagLo0", "DataLo1", "TagLo2", "DataLo3",
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"TagLo4", "DataLo5", "TagLo6", "DataLo7",
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"TagHi0", "DataHi1", "TagHi2", "DataHi3",
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"TagHi4", "DataHi5", "TagHi6", "DataHi7",
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"ErrorEPC", "", "", "", "", "", "", "",
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"DESAVE", "", "", "", "", "", "", "",
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"LLFlag"
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};
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MiscRegFile::MiscRegFile()
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@ -212,7 +222,8 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// Config1
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MiscReg cfg1 = readRegNoEffect(Config1);
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replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, cp.CP0_Config1_MMU);
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replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO,
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cp.CP0_Config1_MMU);
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replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS);
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replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL);
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replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA);
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@ -334,12 +345,18 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// Status
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MiscReg stat = readRegNoEffect(Status);
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// Only CU0 and IE are modified on a reset - everything else needs to be controlled
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// on a per CPU model basis
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// replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1); // Enable CP0 on reset
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// Only CU0 and IE are modified on a reset - everything else needs
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// to be controlled on a per CPU model basis
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// Enable CP0 on reset
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// replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1);
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// Enable ERL bit on a reset
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replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1);
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// Enable BEV bit on a reset
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replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1);
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replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1); // Enable ERL bit on a reset
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replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); // Enable BEV bit on a reset
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setRegNoEffect(Status, stat);
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// Now, create Write Mask for the Status register
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MiscReg stat_Mask = 0xFF78FF17;
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@ -440,7 +457,8 @@ MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
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unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
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? tid : getVPENum(tid);
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DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
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misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]);
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misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),
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miscRegFile[misc_reg][reg_sel]);
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return miscRegFile[misc_reg][reg_sel];
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}
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@ -454,8 +472,10 @@ MiscRegFile::readReg(int reg_idx,
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int misc_reg = reg_idx - Ctrl_Base_DepTag;
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unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
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? tid : getVPENum(tid);
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DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
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misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]);
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DPRINTF(MipsPRA,
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"Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
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misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),
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miscRegFile[misc_reg][reg_sel]);
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switch (misc_reg)
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@ -471,7 +491,9 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
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int misc_reg = reg_idx - Ctrl_Base_DepTag;
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unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
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? tid : getVPENum(tid);
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DPRINTF(MipsPRA, "[tid:%i]: Setting (direct set) CP0 Register:%u Select:%u (%s) to %#x.\n",
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DPRINTF(MipsPRA,
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"[tid:%i]: Setting (direct set) CP0 Register:%u "
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"Select:%u (%s) to %#x.\n",
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tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
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miscRegFile[misc_reg][reg_sel] = val;
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@ -483,7 +505,9 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
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int misc_reg = reg_idx - Ctrl_Base_DepTag;
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unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
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? tid : getVPENum(tid);
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DPRINTF(MipsPRA,"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
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DPRINTF(MipsPRA,
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"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
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tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
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miscRegFile_WriteMask[misc_reg][reg_sel] = val;
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}
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@ -500,7 +524,9 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val,
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int reg_sel = (bankType[misc_reg] == perThreadContext)
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? tid : getVPENum(tid);
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DPRINTF(MipsPRA, "[tid:%i]: Setting CP0 Register:%u Select:%u (%s) to %#x, with effect.\n",
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DPRINTF(MipsPRA,
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"[tid:%i]: Setting CP0 Register:%u "
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"Select:%u (%s) to %#x, with effect.\n",
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tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
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MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
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@ -509,16 +535,28 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val,
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scheduleCP0Update(1);
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}
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/** This method doesn't need to adjust the Control Register Offset since
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it has already been done in the calling method (setRegWithEffect) */
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MiscReg MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
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/**
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* This method doesn't need to adjust the Control Register Offset
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* since it has already been done in the calling method
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* (setRegWithEffect)
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*/
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MiscReg
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MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
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{
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MiscReg retVal = val;
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retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; // Mask off read-only regions
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// Mask off read-only regions
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retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
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MiscReg curVal = miscRegFile[misc_reg][reg_sel];
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curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); // Mask off current alue with inverse mask (clear writeable bits)
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// Mask off current alue with inverse mask (clear writeable bits)
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curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
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retVal |= curVal; // Combine the two
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DPRINTF(MipsPRA,"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, current val: %lx, written val: %x\n",miscRegFile_WriteMask[misc_reg][reg_sel],~miscRegFile_WriteMask[misc_reg][reg_sel],val,miscRegFile[misc_reg][reg_sel],retVal);
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DPRINTF(MipsPRA,
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"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
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"current val: %lx, written val: %x\n",
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miscRegFile_WriteMask[misc_reg][reg_sel],
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~miscRegFile_WriteMask[misc_reg][reg_sel],
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val, miscRegFile[misc_reg][reg_sel], retVal);
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return retVal;
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}
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void
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@ -563,7 +601,8 @@ MiscRegFile::updateCPU()
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}
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MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
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: Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
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: Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu),
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cp0EventType(e_type)
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{ }
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void
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@ -75,7 +75,8 @@ namespace MipsISA
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void clear(unsigned tid_or_vpn = 0);
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void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
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void reset(std::string core_name, unsigned num_threads,
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unsigned num_vpes, BaseCPU *_cpu);
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void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
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@ -98,7 +99,8 @@ namespace MipsISA
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MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
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void setRegMask(int misc_reg, const MiscReg &val, unsigned tid = 0);
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void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
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void setRegNoEffect(int misc_reg, const MiscReg &val,
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unsigned tid = 0);
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//template <class TC>
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void setReg(int misc_reg, const MiscReg &val,
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@ -322,12 +322,14 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
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return readFSReg(miscReg, tc);
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#else
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case MISCREG_HPSTATE:
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//HPSTATE is special because because sometimes in privilege checks for instructions
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//it will read HPSTATE to make sure the priv. level is ok
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//So, we'll just have to tell it it isn't, instead of panicing.
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//HPSTATE is special because because sometimes in privilege
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//checks for instructions it will read HPSTATE to make sure
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//the priv. level is ok So, we'll just have to tell it it
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//isn't, instead of panicing.
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return 0;
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panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
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panic("Accessing Fullsystem register %s in SE mode\n",
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getMiscRegName(miscReg));
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#endif
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}
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@ -584,7 +586,8 @@ void MiscRegFile::setReg(int miscReg,
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//HPSTATE is special because normal trap processing saves HPSTATE when
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//it goes into a trap, and restores it when it returns.
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return;
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panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
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panic("Accessing Fullsystem register %s to %#x in SE mode\n",
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getMiscRegName(miscReg), val);
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#endif
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}
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setRegNoEffect(miscReg, new_val);
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@ -40,22 +40,24 @@ using namespace SparcISA;
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void
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MiscRegFile::checkSoftInt(ThreadContext *tc)
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{
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BaseCPU *cpu = tc->getCpuPtr();
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// If PIL < 14, copy over the tm and sm bits
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if (pil < 14 && softint & 0x10000)
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tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,16);
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cpu->post_interrupt(IT_SOFT_INT, 16);
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else
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tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,16);
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cpu->clear_interrupt(IT_SOFT_INT, 16);
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if (pil < 14 && softint & 0x1)
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tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,0);
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cpu->post_interrupt(IT_SOFT_INT, 0);
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else
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tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,0);
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cpu->clear_interrupt(IT_SOFT_INT, 0);
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// Copy over any of the other bits that are set
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for (int bit = 15; bit > 0; --bit) {
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if (1 << bit & softint && bit > pil)
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tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,bit);
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cpu->post_interrupt(IT_SOFT_INT, bit);
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else
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tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,bit);
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cpu->clear_interrupt(IT_SOFT_INT, bit);
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}
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}
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@ -63,6 +65,8 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
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void
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MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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{
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BaseCPU *cpu = tc->getCpuPtr();
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int64_t time;
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switch (miscReg) {
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/* Full system only ASRs */
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@ -85,7 +89,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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if (!(tick_cmpr & ~mask(63)) && time > 0) {
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if (tickCompare->scheduled())
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tickCompare->deschedule();
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tickCompare->schedule(time * tc->getCpuPtr()->ticks(1));
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tickCompare->schedule(time * cpu->ticks(1));
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}
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panic("writing to TICK compare register %#X\n", val);
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break;
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@ -97,11 +101,11 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
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sTickCompare->deschedule();
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time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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cpu->instCount();
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if (!(stick_cmpr & ~mask(63)) && time > 0) {
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if (sTickCompare->scheduled())
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sTickCompare->deschedule();
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sTickCompare->schedule(time * tc->getCpuPtr()->ticks(1) + curTick);
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sTickCompare->schedule(time * cpu->ticks(1) + curTick);
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}
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DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
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break;
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@ -120,9 +124,9 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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case MISCREG_HINTP:
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setRegNoEffect(miscReg, val);
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if (hintp)
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tc->getCpuPtr()->post_interrupt(IT_HINTP,0);
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cpu->post_interrupt(IT_HINTP, 0);
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else
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tc->getCpuPtr()->clear_interrupt(IT_HINTP,0);
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cpu->clear_interrupt(IT_HINTP, 0);
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break;
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case MISCREG_HTBA:
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@ -134,25 +138,25 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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setRegNoEffect(miscReg, val);
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if (cpu_mondo_head != cpu_mondo_tail)
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||||
tc->getCpuPtr()->post_interrupt(IT_CPU_MONDO,0);
|
||||
cpu->post_interrupt(IT_CPU_MONDO, 0);
|
||||
else
|
||||
tc->getCpuPtr()->clear_interrupt(IT_CPU_MONDO,0);
|
||||
cpu->clear_interrupt(IT_CPU_MONDO, 0);
|
||||
break;
|
||||
case MISCREG_QUEUE_DEV_MONDO_HEAD:
|
||||
case MISCREG_QUEUE_DEV_MONDO_TAIL:
|
||||
setRegNoEffect(miscReg, val);
|
||||
if (dev_mondo_head != dev_mondo_tail)
|
||||
tc->getCpuPtr()->post_interrupt(IT_DEV_MONDO,0);
|
||||
cpu->post_interrupt(IT_DEV_MONDO, 0);
|
||||
else
|
||||
tc->getCpuPtr()->clear_interrupt(IT_DEV_MONDO,0);
|
||||
cpu->clear_interrupt(IT_DEV_MONDO, 0);
|
||||
break;
|
||||
case MISCREG_QUEUE_RES_ERROR_HEAD:
|
||||
case MISCREG_QUEUE_RES_ERROR_TAIL:
|
||||
setRegNoEffect(miscReg, val);
|
||||
if (res_error_head != res_error_tail)
|
||||
tc->getCpuPtr()->post_interrupt(IT_RES_ERROR,0);
|
||||
cpu->post_interrupt(IT_RES_ERROR, 0);
|
||||
else
|
||||
tc->getCpuPtr()->clear_interrupt(IT_RES_ERROR,0);
|
||||
cpu->clear_interrupt(IT_RES_ERROR, 0);
|
||||
break;
|
||||
case MISCREG_QUEUE_NRES_ERROR_HEAD:
|
||||
case MISCREG_QUEUE_NRES_ERROR_TAIL:
|
||||
|
@ -167,11 +171,11 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
|
|||
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
|
||||
hSTickCompare->deschedule();
|
||||
time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
|
||||
tc->getCpuPtr()->instCount();
|
||||
cpu->instCount();
|
||||
if (!(hstick_cmpr & ~mask(63)) && time > 0) {
|
||||
if (hSTickCompare->scheduled())
|
||||
hSTickCompare->deschedule();
|
||||
hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->ticks(1));
|
||||
hSTickCompare->schedule(curTick + time * cpu->ticks(1));
|
||||
}
|
||||
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
|
||||
break;
|
||||
|
@ -181,9 +185,9 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
|
|||
setRegNoEffect(miscReg, val | HPSTATE::id);
|
||||
#if FULL_SYSTEM
|
||||
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
|
||||
tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
|
||||
cpu->post_interrupt(IT_TRAP_LEVEL_ZERO, 0);
|
||||
else
|
||||
tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
|
||||
cpu->clear_interrupt(IT_TRAP_LEVEL_ZERO, 0);
|
||||
#endif
|
||||
break;
|
||||
case MISCREG_HTSTATE:
|
||||
|
@ -200,11 +204,12 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
|
|||
tc->suspend();
|
||||
if (tc->getKernelStats())
|
||||
tc->getKernelStats()->quiesce();
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
|
||||
panic("Invalid write to FS misc register %s\n",
|
||||
getMiscRegName(miscReg));
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -250,7 +255,8 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
|
|||
sys = tc->getSystemPtr();
|
||||
|
||||
temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
|
||||
// Check that the CPU array is fully populated (by calling getNumCPus())
|
||||
// Check that the CPU array is fully populated
|
||||
// (by calling getNumCPus())
|
||||
assert(sys->getNumCPUs() > tc->readCpuId());
|
||||
|
||||
temp |= tc->readCpuId() << STS::shft_id;
|
||||
|
@ -280,16 +286,6 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
|
|||
panic("Invalid read to FS misc register\n");
|
||||
}
|
||||
}
|
||||
/*
|
||||
In Niagra STICK==TICK so this isn't needed
|
||||
case MISCREG_STICK:
|
||||
SparcSystem *sys;
|
||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||
assert(sys != NULL);
|
||||
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
|
||||
*/
|
||||
|
||||
|
||||
|
||||
void
|
||||
MiscRegFile::processTickCompare(ThreadContext *tc)
|
||||
|
|
Loading…
Reference in a new issue