config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams() is the practice of appending to SimObjectVectors which have already been assigned as children. This practice sidesteps the assignment operation for those appended SimObjects, which is where parent/child relationships are typically established. This patch reworks the config scripts that use append() on SimObjectVectors, which all happen to be in the x86 system configuration. At some point in the future, I hope to make SimObjectVectors immutable (by deriving from tuple rather than list), at which time this patch will be necessary for correct operation. For now, it just avoids some of the warning messages that get printed in adoptOrphanParams().
This commit is contained in:
Steve Reinhardt
parent
8a652f9871
commit
19bb896bfe
3 changed files with 32 additions and 39 deletions
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@ -306,7 +306,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
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def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port;
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return IO_address_space_base + port
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def connectX86ClassicSystem(x86_sys):
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x86_sys.membus = MemBus(bus_id=1)
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@ -375,27 +375,29 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
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self.smbios_table.structures = structures
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# Set up the Intel MP table
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base_entries = []
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ext_entries = []
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for i in xrange(numCPUs):
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bp = X86IntelMPProcessor(
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local_apic_id = i,
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local_apic_version = 0x14,
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enable = True,
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bootstrap = (i == 0))
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self.intel_mp_table.add_entry(bp)
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base_entries.append(bp)
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io_apic = X86IntelMPIOAPIC(
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id = numCPUs,
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version = 0x11,
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enable = True,
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address = 0xfec00000)
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self.pc.south_bridge.io_apic.apic_id = io_apic.id
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self.intel_mp_table.add_entry(io_apic)
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base_entries.append(io_apic)
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isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
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self.intel_mp_table.add_entry(isa_bus)
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base_entries.append(isa_bus)
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pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
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self.intel_mp_table.add_entry(pci_bus)
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base_entries.append(pci_bus)
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connect_busses = X86IntelMPBusHierarchy(bus_id=0,
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subtractive_decode=True, parent_bus=1)
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self.intel_mp_table.add_entry(connect_busses)
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ext_entries.append(connect_busses)
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pci_dev4_inta = X86IntelMPIOIntAssignment(
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interrupt_type = 'INT',
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polarity = 'ConformPolarity',
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@ -404,7 +406,7 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
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source_bus_irq = 0 + (4 << 2),
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dest_io_apic_id = io_apic.id,
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dest_io_apic_intin = 16)
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self.intel_mp_table.add_entry(pci_dev4_inta);
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base_entries.append(pci_dev4_inta)
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def assignISAInt(irq, apicPin):
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assign_8259_to_apic = X86IntelMPIOIntAssignment(
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interrupt_type = 'ExtInt',
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@ -414,7 +416,7 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
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source_bus_irq = irq,
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dest_io_apic_id = io_apic.id,
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dest_io_apic_intin = 0)
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self.intel_mp_table.add_entry(assign_8259_to_apic)
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base_entries.append(assign_8259_to_apic)
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assign_to_apic = X86IntelMPIOIntAssignment(
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interrupt_type = 'INT',
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polarity = 'ConformPolarity',
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@ -423,11 +425,13 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
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source_bus_irq = irq,
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dest_io_apic_id = io_apic.id,
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dest_io_apic_intin = apicPin)
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self.intel_mp_table.add_entry(assign_to_apic)
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base_entries.append(assign_to_apic)
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assignISAInt(0, 2)
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assignISAInt(1, 1)
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for i in range(3, 15):
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assignISAInt(i, i)
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self.intel_mp_table.base_entries = base_entries
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self.intel_mp_table.ext_entries = ext_entries
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def setWorkCountOptions(system, options):
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if options.work_item_id != None:
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@ -456,17 +460,15 @@ def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
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# just to avoid corner cases.
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assert(self.physmem.range.second.getValue() >= 0x200000)
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# Mark the first megabyte of memory as reserved
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self.e820_table.entries.append(X86E820Entry(
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addr = 0,
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size = '1MB',
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range_type = 2))
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# Mark the rest as available
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self.e820_table.entries.append(X86E820Entry(
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addr = 0x100000,
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self.e820_table.entries = \
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[
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# Mark the first megabyte of memory as reserved
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X86E820Entry(addr = 0, size = '1MB', range_type = 2),
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# Mark the rest as available
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X86E820Entry(addr = 0x100000,
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size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
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range_type = 1))
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range_type = 1)
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]
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# Command line
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self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
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@ -50,4 +50,4 @@ class X86E820Table(SimObject):
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type = 'X86E820Table'
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cxx_class = 'X86ISA::E820Table'
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entries = VectorParam.X86E820Entry([], 'entries for the e820 table')
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entries = VectorParam.X86E820Entry('entries for the e820 table')
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@ -57,9 +57,6 @@ class SouthBridge(SimObject):
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_pit = I8254(pio_addr=x86IOAddress(0x40))
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_speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
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_io_apic = I82094AA(pio_addr=0xFEC00000)
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# This is to make sure the interrupt lines are instantiated. Don't use
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# it for anything directly.
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int_lines = VectorParam.X86IntLine([], "Interrupt lines")
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pic1 = Param.I8259(_pic1, "Master PIC")
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pic2 = Param.I8259(_pic2, "Slave PIC")
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@ -70,9 +67,6 @@ class SouthBridge(SimObject):
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speaker = Param.PcSpeaker(_speaker, "PC speaker")
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io_apic = Param.I82094AA(_io_apic, "I/O APIC")
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def connectPins(self, source, sink):
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self.int_lines.append(X86IntLine(source=source, sink=sink))
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# IDE controller
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ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
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ide.BAR0 = 0x1f0
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@ -93,19 +87,16 @@ class SouthBridge(SimObject):
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def attachIO(self, bus):
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# Route interupt signals
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self.connectPins(self.pic1.output, self.io_apic.pin(0))
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self.connectPins(self.pic2.output, self.pic1.pin(2))
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self.connectPins(self.cmos.int_pin, self.pic2.pin(0))
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self.connectPins(self.pit.int_pin, self.pic1.pin(0))
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self.connectPins(self.pit.int_pin, self.io_apic.pin(2))
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# self.connectPins(self.keyboard.keyboard_int_pin,
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# self.pic1.pin(1))
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self.connectPins(self.keyboard.keyboard_int_pin,
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self.io_apic.pin(1))
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# self.connectPins(self.keyboard.mouse_int_pin,
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# self.pic2.pin(4))
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self.connectPins(self.keyboard.mouse_int_pin,
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self.io_apic.pin(12))
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self.int_lines = \
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[X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)),
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X86IntLine(source=self.pic2.output, sink=self.pic1.pin(2)),
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X86IntLine(source=self.cmos.int_pin, sink=self.pic2.pin(0)),
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X86IntLine(source=self.pit.int_pin, sink=self.pic1.pin(0)),
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X86IntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)),
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X86IntLine(source=self.keyboard.keyboard_int_pin,
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sink=self.io_apic.pin(1)),
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X86IntLine(source=self.keyboard.mouse_int_pin,
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sink=self.io_apic.pin(12))]
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# Tell the devices about each other
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self.pic1.slave = self.pic2
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self.speaker.i8254 = self.pit
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