diff --git a/build_opts/NOISA b/build_opts/NOISA deleted file mode 100644 index dd1f82a78..000000000 --- a/build_opts/NOISA +++ /dev/null @@ -1,2 +0,0 @@ -TARGET_ISA = 'no' -CPU_MODELS = 'no' diff --git a/build_opts/NULL b/build_opts/NULL new file mode 100644 index 000000000..5d85833f3 --- /dev/null +++ b/build_opts/NULL @@ -0,0 +1,2 @@ +TARGET_ISA = 'null' +CPU_MODELS = '' diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript index f2edc805d..3dfc509a4 100644 --- a/src/arch/generic/SConscript +++ b/src/arch/generic/SConscript @@ -28,4 +28,7 @@ Import('*') +if env['TARGET_ISA'] == 'null': + Return() + Source('decode_cache.cc') diff --git a/src/arch/noisa/SConsopts b/src/arch/noisa/SConsopts deleted file mode 100644 index fbfcf05c9..000000000 --- a/src/arch/noisa/SConsopts +++ /dev/null @@ -1,4 +0,0 @@ - -Import('*') - -all_isa_list.append('no') diff --git a/src/arch/noisa/cpu_dummy.hh b/src/arch/noisa/cpu_dummy.hh deleted file mode 100644 index 0d494d6a5..000000000 --- a/src/arch/noisa/cpu_dummy.hh +++ /dev/null @@ -1,7 +0,0 @@ - -class BaseCPU -{ - public: - static int numSimulatedInsts() { return 0; } - static int numSimulatedOps() { return 0; } -}; diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript new file mode 100644 index 000000000..e64b69c41 --- /dev/null +++ b/src/arch/null/SConscript @@ -0,0 +1,43 @@ +# -*- mode:python -*- + +# Copyright (c) 2013 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Hansson + +Import('*') + +if env['TARGET_ISA'] == 'null': + Source('cpu_dummy.cc') diff --git a/src/arch/null/SConsopts b/src/arch/null/SConsopts new file mode 100644 index 000000000..e377564de --- /dev/null +++ b/src/arch/null/SConsopts @@ -0,0 +1,42 @@ +# -*- mode:python -*- + +# Copyright (c) 2013 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Hansson + +Import('*') + +all_isa_list.append('null') diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc new file mode 100644 index 000000000..4c78bf777 --- /dev/null +++ b/src/arch/null/cpu_dummy.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +/** + * Provide the actual storage for maxThreadsPerCPU which is declared + * extern and normally provided by src/cpu/base.cc + */ +int maxThreadsPerCPU = 1; diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh new file mode 100644 index 000000000..ed6f6d1d6 --- /dev/null +++ b/src/arch/null/cpu_dummy.hh @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +#ifndef __ARCH_NULL_CPU_DUMMY_HH__ +#define __ARCH_NULL_CPU_DUMMY_HH__ + +#include "sim/core.hh" + +class BaseCPU +{ + public: + static int numSimulatedInsts() { return 0; } + static int numSimulatedOps() { return 0; } +}; + +#endif // __ARCH_NULL_CPU_DUMMY_HH__ diff --git a/src/arch/null/isa_traits.hh b/src/arch/null/isa_traits.hh new file mode 100644 index 000000000..d09b1e876 --- /dev/null +++ b/src/arch/null/isa_traits.hh @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +#ifndef __ARCH_NULL_ISA_TRAITS_HH__ +#define __ARCH_NULL_ISA_TRAITS_HH__ + +#include "base/types.hh" + +namespace LittleEndianGuest {} + +namespace NullISA +{ + using namespace LittleEndianGuest; + + const Addr PageShift = 12; + const Addr PageBytes = ULL(1) << PageShift; + + const int LogVMPageSize = 12; // 4K bytes + const int VMPageSize = (1 << LogVMPageSize); + +} + +#endif //__ARCH_NULL_ISA_TRAITS_HH__ diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh new file mode 100644 index 000000000..f33b7e5bd --- /dev/null +++ b/src/arch/null/registers.hh @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +#ifndef __ARCH_NULL_REGISTERS_HH__ +#define __ARCH_NULL_REGISTERS_HH__ + +#include "base/types.hh" + +namespace NullISA { + +typedef uint64_t IntReg; +typedef uint32_t FloatRegBits; +typedef float FloatReg; +typedef uint64_t MiscReg; + +} + +#endif // __ARCH_NULL_REGISTERS_HH__ diff --git a/src/arch/null/remote_gdb.hh b/src/arch/null/remote_gdb.hh new file mode 100644 index 000000000..dddebce7d --- /dev/null +++ b/src/arch/null/remote_gdb.hh @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +#ifndef __ARCH_NULL_REMOTE_GDB_HH__ +#define __ARCH_NULL_REMOTE_GDB_HH__ + +class ThreadContext; + +class BaseRemoteGDB +{ + + public: + + bool breakpoint() { return false; } + void replaceThreadContext(ThreadContext *tc) {} + + virtual ~BaseRemoteGDB() {} +}; + +#endif // __ARCH_NULL_REMOTE_GDB_H__ diff --git a/src/arch/null/types.hh b/src/arch/null/types.hh new file mode 100644 index 000000000..b62b8f2ff --- /dev/null +++ b/src/arch/null/types.hh @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +#ifndef __ARCH_NULL_TYPES_HH__ +#define __ARCH_NULL_TYPES_HH__ + +#include "arch/generic/types.hh" + +namespace NullISA +{ + typedef uint32_t MachInst; + + class PCState : public GenericISA::UPCState + { + protected: + + typedef GenericISA::UPCState Base; + }; + +} + +#endif // __ARCH_NULL_TYPES_HH__ diff --git a/src/arch/null/utility.hh b/src/arch/null/utility.hh new file mode 100644 index 000000000..cf65ef5cd --- /dev/null +++ b/src/arch/null/utility.hh @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +#ifndef __ARCH_NULL_UTILITY_HH__ +#define __ARCH_NULL_UTILITY_HH__ + +#include "base/types.hh" +#include "cpu/thread_context.hh" + +namespace NullISA { + +inline uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, + bool fp) { return 0; } + +inline void startupCPU(ThreadContext *tc, int cpuId) {} + +} + +#endif // __ARCH_NULL_UTILITY_HH__ diff --git a/src/base/SConscript b/src/base/SConscript index b2a348f15..8c32bb3c9 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -52,7 +52,7 @@ Source('output.cc') Source('pollevent.cc') Source('random.cc') Source('random_mt.cc') -if env['TARGET_ISA'] != 'no': +if env['TARGET_ISA'] != 'null': Source('remote_gdb.cc') Source('socket.cc') Source('statistics.cc') diff --git a/src/cpu/SConscript b/src/cpu/SConscript index c52dbc53b..999de1e49 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -30,7 +30,9 @@ Import('*') -if env['TARGET_ISA'] == 'no': +if env['TARGET_ISA'] == 'null': + SimObject('IntrControl.py') + Source('intr_control_noisa.cc') Return() ################################################################# diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 9e7198763..540c72833 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -48,11 +48,16 @@ #include +// Before we do anything else, check if this build is the NULL ISA, +// and if so stop here +#include "config/the_isa.hh" +#if THE_ISA == NULL_ISA +#include "arch/null/cpu_dummy.hh" +#else #include "arch/interrupts.hh" #include "arch/isa_traits.hh" #include "arch/microcode_rom.hh" #include "base/statistics.hh" -#include "config/the_isa.hh" #include "mem/mem_object.hh" #include "sim/eventq.hh" #include "sim/full_system.hh" @@ -476,4 +481,6 @@ class BaseCPU : public MemObject Stats::Scalar numWorkItemsCompleted; }; +#endif // THE_ISA == NULL_ISA + #endif // __CPU_BASE_HH__ diff --git a/src/cpu/intr_control_noisa.cc b/src/cpu/intr_control_noisa.cc new file mode 100644 index 000000000..ff49976d0 --- /dev/null +++ b/src/cpu/intr_control_noisa.cc @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Ron Dreslinski + */ + +#include "cpu/intr_control.hh" + +using namespace std; + +IntrControl::IntrControl(const Params *p) + : SimObject(p), sys(p->sys) +{} + +void +IntrControl::post(int cpu_id, int int_num, int index) +{ +} + +void +IntrControl::clear(int cpu_id, int int_num, int index) +{ +} + +IntrControl * +IntrControlParams::create() +{ + return new IntrControl(this); +} diff --git a/src/dev/SConscript b/src/dev/SConscript index cba821f87..1bcddb6ee 100644 --- a/src/dev/SConscript +++ b/src/dev/SConscript @@ -31,7 +31,7 @@ Import('*') -if env['TARGET_ISA'] == 'no': +if env['TARGET_ISA'] == 'null': Return() SimObject('BadDevice.py') diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 02eb8a113..7da70c482 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -32,7 +32,9 @@ #include #include +#ifdef SINIC_VTOPHYS #include "arch/vtophys.hh" +#endif #include "base/compiler.hh" #include "base/debug.hh" #include "base/inet.hh" diff --git a/src/kern/SConscript b/src/kern/SConscript index 38734e650..2f4d70a48 100644 --- a/src/kern/SConscript +++ b/src/kern/SConscript @@ -30,7 +30,7 @@ Import('*') -if env['TARGET_ISA'] == 'no': +if env['TARGET_ISA'] == 'null': Return() Source('kernel_stats.cc') diff --git a/src/mem/SConscript b/src/mem/SConscript index ca89418b5..02d0aee73 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -36,11 +36,15 @@ if env['HAVE_PROTOBUF']: SimObject('CommMonitor.py') Source('comm_monitor.cc') +SimObject('AbstractMemory.py') SimObject('AddrMapper.py') SimObject('Bridge.py') SimObject('Bus.py') SimObject('MemObject.py') +SimObject('SimpleMemory.py') +SimObject('SimpleDRAM.py') +Source('abstract_mem.cc') Source('addr_mapper.cc') Source('bridge.cc') Source('bus.cc') @@ -53,18 +57,14 @@ Source('port.cc') Source('packet_queue.cc') Source('tport.cc') Source('port_proxy.cc') -Source('fs_translating_port_proxy.cc') -Source('se_translating_port_proxy.cc') +Source('simple_mem.cc') +Source('physical.cc') +Source('simple_dram.cc') -if env['TARGET_ISA'] != 'no': - SimObject('AbstractMemory.py') - SimObject('SimpleMemory.py') - SimObject('SimpleDRAM.py') - Source('abstract_mem.cc') - Source('simple_mem.cc') +if env['TARGET_ISA'] != 'null': + Source('fs_translating_port_proxy.cc') + Source('se_translating_port_proxy.cc') Source('page_table.cc') - Source('physical.cc') - Source('simple_dram.cc') DebugFlag('BaseBus') DebugFlag('BusAddrRanges') diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 8323602d2..a4fbe04c0 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -30,9 +30,6 @@ Import('*') -if env['TARGET_ISA'] == 'no': - Return() - SimObject('BaseCache.py') Source('base.cc') diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 03b4d5dc1..af324527f 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -45,8 +45,6 @@ * Definition of BaseCache functions. */ -#include "cpu/base.hh" -#include "cpu/smt.hh" #include "debug/Cache.hh" #include "debug/Drain.hh" #include "mem/cache/tags/fa_lru.hh" diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript index 2310940c1..61291f715 100644 --- a/src/mem/cache/prefetch/SConscript +++ b/src/mem/cache/prefetch/SConscript @@ -30,8 +30,6 @@ Import('*') -if env['TARGET_ISA'] == 'no': - Return() SimObject('Prefetcher.py') Source('base.cc') diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index de835c1d0..dca8d3bd8 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -30,9 +30,6 @@ Import('*') -if env['TARGET_ISA'] == 'no': - Return() - SimObject('Tags.py') Source('base.cc') diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc index d9909f5de..947bd05de 100644 --- a/src/mem/cache/tags/base.cc +++ b/src/mem/cache/tags/base.cc @@ -46,6 +46,7 @@ * Definitions of BaseTags. */ +#include "config/the_isa.hh" #include "cpu/smt.hh" //maxThreadsPerCPU #include "mem/cache/tags/base.hh" #include "mem/cache/base.hh" diff --git a/src/mem/fs_translating_port_proxy.cc b/src/mem/fs_translating_port_proxy.cc index 8fb9b91ef..52e8b49d8 100644 --- a/src/mem/fs_translating_port_proxy.cc +++ b/src/mem/fs_translating_port_proxy.cc @@ -46,6 +46,7 @@ * Port object definitions. */ +#include "arch/vtophys.hh" #include "base/chunk_generator.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" diff --git a/src/mem/fs_translating_port_proxy.hh b/src/mem/fs_translating_port_proxy.hh index 2a9223050..c8f099d2c 100644 --- a/src/mem/fs_translating_port_proxy.hh +++ b/src/mem/fs_translating_port_proxy.hh @@ -59,9 +59,10 @@ #ifndef __MEM_FS_PORT_PROXY_HH__ #define __MEM_FS_PORT_PROXY_HH__ -#include "arch/vtophys.hh" #include "mem/port_proxy.hh" +class ThreadContext; + /** * A TranslatingPortProxy in FS mode translates a virtual address to a * physical address and then calls the read/write functions of the diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh index f1e01c385..1213daafa 100644 --- a/src/mem/port_proxy.hh +++ b/src/mem/port_proxy.hh @@ -60,7 +60,7 @@ #define __MEM_PORT_PROXY_HH__ #include "config/the_isa.hh" -#if THE_ISA != NO_ISA +#if THE_ISA != NULL_ISA #include "arch/isa_traits.hh" #endif @@ -127,7 +127,7 @@ class PortProxy template void write(Addr address, T data) const; -#if THE_ISA != NO_ISA +#if THE_ISA != NULL_ISA /** * Read sizeof(T) bytes from address and return as object T. * Performs Guest to Host endianness transform. @@ -161,7 +161,7 @@ PortProxy::write(Addr address, T data) const writeBlob(address, (uint8_t*)&data, sizeof(T)); } -#if THE_ISA != NO_ISA +#if THE_ISA != NULL_ISA template T PortProxy::readGtoH(Addr address) const diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript index 086c2f764..b655caa7d 100644 --- a/src/mem/ruby/SConscript +++ b/src/mem/ruby/SConscript @@ -37,7 +37,7 @@ import SCons Import('*') -if env['TARGET_ISA'] == 'no': +if env['TARGET_ISA'] == 'null': Return() if env['PROTOCOL'] == 'None': diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc index f534623f8..fe849ec88 100644 --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@ -34,16 +34,19 @@ #include "base/inifile.hh" #include "base/output.hh" +#include "config/the_isa.hh" +#if THE_ISA != NULL_ISA #include "dev/etherdevice.hh" #include "dev/etherobject.hh" +#endif #include "mem/mem_object.hh" -#include "mem/port.hh" #include "python/swig/pyobject.hh" #include "sim/full_system.hh" #include "sim/sim_object.hh" using namespace std; +#if THE_ISA != NULL_ISA EtherInt * lookupEthPort(SimObject *so, const std::string &name, int i) { @@ -61,6 +64,7 @@ lookupEthPort(SimObject *so, const std::string &name, int i) p = ed->getEthPort(name, i); return p; } +#endif /** * Connect the described MemObject ports. Called from Python via SWIG. @@ -71,6 +75,7 @@ int connectPorts(SimObject *o1, const std::string &name1, int i1, SimObject *o2, const std::string &name2, int i2) { +#if THE_ISA != NULL_ISA if (FullSystem) { EtherObject *eo1, *eo2; EtherDevice *ed1, *ed2; @@ -92,6 +97,7 @@ connectPorts(SimObject *o1, const std::string &name1, int i1, } } } +#endif MemObject *mo1, *mo2; mo1 = dynamic_cast(o1); mo2 = dynamic_cast(o2); diff --git a/src/sim/SConscript b/src/sim/SConscript index 90d77848b..850af230e 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -33,9 +33,9 @@ Import('*') SimObject('BaseTLB.py') SimObject('ClockedObject.py') SimObject('Root.py') -SimObject('InstTracer.py') SimObject('ClockDomain.py') SimObject('VoltageDomain.py') +SimObject('System.py') Source('arguments.cc') Source('async.cc') @@ -51,19 +51,17 @@ Source('sim_events.cc') Source('sim_object.cc') Source('simulate.cc') Source('stat_control.cc') -Source('syscall_emul.cc') Source('clock_domain.cc') Source('voltage_domain.cc') +Source('system.cc') -if env['TARGET_ISA'] != 'no': +if env['TARGET_ISA'] != 'null': + SimObject('InstTracer.py') SimObject('Process.py') - SimObject('System.py') Source('faults.cc') Source('process.cc') Source('pseudo_inst.cc') - Source('system.cc') - -if env['TARGET_ISA'] != 'no': + Source('syscall_emul.cc') Source('tlb.cc') DebugFlag('Checkpoint') diff --git a/src/sim/arguments.hh b/src/sim/arguments.hh index fad955999..58a43852c 100644 --- a/src/sim/arguments.hh +++ b/src/sim/arguments.hh @@ -33,7 +33,6 @@ #include -#include "arch/vtophys.hh" #include "base/refcnt.hh" #include "base/types.hh" #include "mem/fs_translating_port_proxy.hh" diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc index 5429861d6..7a8d48ae2 100644 --- a/src/sim/stat_control.cc +++ b/src/sim/stat_control.cc @@ -52,13 +52,7 @@ #include "base/hostinfo.hh" #include "base/statistics.hh" #include "base/time.hh" -#include "config/the_isa.hh" -#if THE_ISA == NO_ISA -#include "arch/noisa/cpu_dummy.hh" -#else #include "cpu/base.hh" -#endif - #include "sim/eventq_impl.hh" #include "sim/stat_control.hh" diff --git a/src/sim/system.cc b/src/sim/system.cc index 24f9dfbad..7de483216 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -48,7 +48,6 @@ #include "arch/isa_traits.hh" #include "arch/remote_gdb.hh" #include "arch/utility.hh" -#include "arch/vtophys.hh" #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "base/str.hh" @@ -228,6 +227,7 @@ System::registerThreadContext(ThreadContext *tc, int assigned) threadContexts[id] = tc; _numContexts++; +#if THE_ISA != NULL_ISA int port = getRemoteGDBPort(); if (port) { RemoteGDB *rgdb = new RemoteGDB(this, tc); @@ -243,6 +243,7 @@ System::registerThreadContext(ThreadContext *tc, int assigned) remoteGDB[id] = rgdb; } +#endif activeCpus.push_back(false); diff --git a/src/sim/system.hh b/src/sim/system.hh index 5058e7b26..5b166eabf 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -184,7 +184,9 @@ class System : public MemObject */ unsigned int cacheLineSize() const { return _cacheLineSize; } +#if THE_ISA != NULL_ISA PCEventQueue pcEventQueue; +#endif std::vector threadContexts; int _numContexts; @@ -380,11 +382,13 @@ class System : public MemObject { Addr addr = 0; // initialize only to avoid compiler warning +#if THE_ISA != NULL_ISA if (symtab->findAddress(lbl, addr)) { T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), std::forward(args)...); return ev; } +#endif return NULL; } diff --git a/src/unittest/SConscript b/src/unittest/SConscript index 841cbb8a6..4cb14a290 100644 --- a/src/unittest/SConscript +++ b/src/unittest/SConscript @@ -30,9 +30,6 @@ Import('*') -if env['TARGET_ISA'] == 'no': - Return() - Source('unittest.cc') UnitTest('bitvectest', 'bitvectest.cc') diff --git a/util/regress b/util/regress index b17da8797..2ed2b6970 100755 --- a/util/regress +++ b/util/regress @@ -45,6 +45,7 @@ add_option('--builds', 'ALPHA_MOESI_CMP_directory,' \ 'ALPHA_MOESI_CMP_token,' \ 'MIPS,' \ + 'NULL,' \ 'POWER,' \ 'SPARC,' \ 'X86,X86_MESI_CMP_directory,' \