x86 regressions: stats update due to new x87 instructions
This commit is contained in:
Nilay Vaish
parent
e9fa54de58
commit
1945f9963d
73 changed files with 3326 additions and 3333 deletions
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@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
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[system.cpu]
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type=DerivO3CPU
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children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
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children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
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BTBEntries=4096
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BTBTagSize=16
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LFSTSize=1024
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@ -78,7 +78,6 @@ iewToFetchDelay=1
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iewToRenameDelay=1
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instShiftAmt=2
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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issueToExecuteDelay=1
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issueWidth=8
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itb=system.cpu.itb
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@ -465,9 +464,6 @@ int_master=system.membus.slave[2]
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int_slave=system.membus.master[2]
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pio=system.membus.master[1]
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[system.cpu.isa]
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type=X86ISA
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[system.cpu.itb]
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type=X86TLB
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children=walker
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@ -528,7 +524,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/gzip
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executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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@ -1,4 +1,3 @@
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warn: Sockets disabled, not accepting gdb connections
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warn: instruction 'fnstcw_Mw' unimplemented
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warn: instruction 'fldcw_Mw' unimplemented
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hack: be nice to actually delete the event here
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@ -1,9 +1,11 @@
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Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
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Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 30 2012 11:14:29
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gem5 started Oct 30 2012 16:17:19
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gem5 executing on u200540-lin
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gem5 compiled Dec 30 2012 00:35:18
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gem5 started Dec 30 2012 00:35:30
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gem5 executing on ribera.cs.wisc.edu
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command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -40,4 +42,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 607235830000 because target called exit()
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Exiting @ tick 607445544000 because target called exit()
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File diff suppressed because it is too large
Load diff
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@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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boot_osflags=a
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clock=1
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clock=1000
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
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[system.cpu.dtb.walker]
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type=X86PagetableWalker
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clock=1
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clock=500
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system=system
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port=system.membus.slave[4]
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[system.cpu.interrupts]
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type=X86LocalApic
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clock=1
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clock=500
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int_latency=1000
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pio_addr=2305843009213693952
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pio_latency=100000
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@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
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[system.cpu.itb.walker]
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type=X86PagetableWalker
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clock=1
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clock=500
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system=system
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port=system.membus.slave[3]
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@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
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[system.physmem]
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type=SimpleMemory
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clock=1
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bandwidth=73.000000
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clock=1000
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conf_table_reported=false
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file=
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in_addr_map=true
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latency=30000
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latency_var=0
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@ -1,4 +1,3 @@
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warn: Sockets disabled, not accepting gdb connections
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warn: instruction 'fnstcw_Mw' unimplemented
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warn: instruction 'fldcw_Mw' unimplemented
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hack: be nice to actually delete the event here
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@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomi
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Sep 10 2012 22:29:00
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gem5 started Sep 10 2012 22:29:07
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gem5 compiled Dec 30 2012 00:35:18
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gem5 started Dec 30 2012 00:35:29
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gem5 executing on ribera.cs.wisc.edu
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command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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@ -41,4 +41,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 963992671000 because target called exit()
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Exiting @ tick 963992671500 because target called exit()
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@ -1,59 +1,59 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.963993 # Number of seconds simulated
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sim_ticks 963992671000 # Number of ticks simulated
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final_tick 963992671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_ticks 963992671500 # Number of ticks simulated
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final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 939514 # Simulator instruction rate (inst/s)
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host_op_rate 1731105 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1029157174 # Simulator tick rate (ticks/s)
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host_mem_usage 266280 # Number of bytes of host memory used
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host_seconds 936.68 # Real time elapsed on the host
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host_inst_rate 908989 # Simulator instruction rate (inst/s)
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host_op_rate 1674860 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 995719480 # Simulator tick rate (ticks/s)
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host_mem_usage 267620 # Number of bytes of host memory used
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host_seconds 968.14 # Real time elapsed on the host
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sim_insts 880025278 # Number of instructions simulated
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sim_ops 1621493926 # Number of ops (including micro ops) simulated
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sim_ops 1621493927 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1842452909 # Number of bytes read from this memory
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system.physmem.bytes_read::total 11334586469 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory
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system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 864451002 # Number of bytes written to this memory
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system.physmem.bytes_written::total 864451002 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 419042121 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1605558816 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 9846686438 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 11757959173 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 9846686438 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 9846686438 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 896740220 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 896740220 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 9846686438 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2808012955 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 12654699393 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.num_writes::cpu.data 188186058 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 188186058 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 9846686433 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1911272734 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 11757959167 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 9846686433 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 9846686433 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 896740222 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 896740222 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 9846686433 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2808012956 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 12654699389 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.workload.num_syscalls 48 # Number of system calls
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system.cpu.numCycles 1927985343 # number of cpu cycles simulated
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system.cpu.numCycles 1927985344 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 880025278 # Number of instructions committed
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system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses
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system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1621354436 # number of integer instructions
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system.cpu.num_int_insts 1621354438 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written
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system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 607228178 # number of memory refs
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system.cpu.num_mem_refs 607228179 # number of memory refs
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system.cpu.num_load_insts 419042121 # Number of load instructions
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system.cpu.num_store_insts 188186057 # Number of store instructions
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system.cpu.num_store_insts 188186058 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1927985343 # Number of busy cycles
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system.cpu.num_busy_cycles 1927985344 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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boot_osflags=a
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clock=1
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clock=1000
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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@ -61,21 +61,22 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=2
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block_size=64
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clock=1
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=2
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=10
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=2
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size=262144
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subblock_size=0
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system=system
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tgts_per_mshr=5
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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write_buffers=8
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@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
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[system.cpu.dtb.walker]
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type=X86PagetableWalker
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clock=1
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clock=500
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system=system
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port=system.cpu.toL2Bus.slave[3]
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@ -99,21 +100,22 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=2
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block_size=64
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clock=1
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=2
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=10
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=2
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size=131072
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subblock_size=0
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system=system
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tgts_per_mshr=5
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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write_buffers=8
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@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
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[system.cpu.interrupts]
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type=X86LocalApic
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clock=1
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clock=500
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int_latency=1000
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pio_addr=2305843009213693952
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pio_latency=100000
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@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
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[system.cpu.itb.walker]
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type=X86PagetableWalker
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clock=1
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clock=500
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system=system
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port=system.cpu.toL2Bus.slave[2]
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[system.cpu.l2cache]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=2
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assoc=8
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block_size=64
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clock=1
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=20
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is_top_level=false
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latency=10000
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max_miss_count=0
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mshrs=10
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=20
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size=2097152
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subblock_size=0
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system=system
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tgts_per_mshr=5
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tgts_per_mshr=12
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trace_addr=0
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two_queue=false
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write_buffers=8
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@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
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[system.cpu.toL2Bus]
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type=CoherentBus
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block_size=64
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clock=1000
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clock=500
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header_cycles=1
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use_default_range=false
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width=8
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width=32
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master=system.cpu.l2cache.cpu_side
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slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
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@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
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[system.physmem]
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type=SimpleMemory
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clock=1
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bandwidth=73.000000
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clock=1000
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conf_table_reported=false
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file=
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in_addr_map=true
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latency=30000
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latency_var=0
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@ -1,4 +1,3 @@
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warn: Sockets disabled, not accepting gdb connections
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warn: instruction 'fnstcw_Mw' unimplemented
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warn: instruction 'fldcw_Mw' unimplemented
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hack: be nice to actually delete the event here
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@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timin
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gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
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gem5 started Sep 10 2012 22:43:43
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gem5 compiled Dec 30 2012 00:35:18
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gem5 started Dec 30 2012 00:35:29
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -41,4 +41,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 1801979679000 because target called exit()
|
||||
Exiting @ tick 1800193397000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.800193 # Number of seconds simulated
|
||||
sim_ticks 1800193396000 # Number of ticks simulated
|
||||
final_tick 1800193396000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1800193397000 # Number of ticks simulated
|
||||
final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 332254 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 612196 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 679663607 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227800 # Number of bytes of host memory used
|
||||
host_seconds 2648.65 # Real time elapsed on the host
|
||||
host_inst_rate 477976 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 880696 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 977754272 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 276196 # Number of bytes of host memory used
|
||||
host_seconds 1841.15 # Real time elapsed on the host
|
||||
sim_insts 880025278 # Number of instructions simulated
|
||||
sim_ops 1621493926 # Number of ops (including micro ops) simulated
|
||||
sim_ops 1621493927 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
|
||||
|
|
@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 25668 # To
|
|||
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 3600386792 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3600386794 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 880025278 # Number of instructions committed
|
||||
system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses
|
||||
system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1621354436 # number of integer instructions
|
||||
system.cpu.num_int_insts 1621354438 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 607228178 # number of memory refs
|
||||
system.cpu.num_mem_refs 607228179 # number of memory refs
|
||||
system.cpu.num_load_insts 419042121 # Number of load instructions
|
||||
system.cpu.num_store_insts 188186057 # Number of store instructions
|
||||
system.cpu.num_store_insts 188186058 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3600386792 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3600386794 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 4 # number of replacements
|
||||
|
|
@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 437952 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.905744 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 771786000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.905744 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 606786130 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 606786130 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 606786130 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 606786130 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 606786131 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
|
||||
|
|
@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 6851581000
|
|||
system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 607228178 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 607228178 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 607228178 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 607228178 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
|
||||
|
|
@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 2532 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22211.029339 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21021.301366 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21021.301355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 546.528757 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.019629 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,7 +78,6 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -465,9 +464,6 @@ int_master=system.membus.slave[2]
|
|||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -528,9 +524,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 16:29:18
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:35:30
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -23,4 +25,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 66000220500 because target called exit()
|
||||
Exiting @ tick 65982862500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
|
|
@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:54:55
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:45:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -25,4 +25,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 168950039000 because target called exit()
|
||||
Exiting @ tick 168950039500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,59 +1,59 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.168950 # Number of seconds simulated
|
||||
sim_ticks 168950039000 # Number of ticks simulated
|
||||
final_tick 168950039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 168950039500 # Number of ticks simulated
|
||||
final_tick 168950039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 917389 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1615374 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 981038557 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 400492 # Number of bytes of host memory used
|
||||
host_seconds 172.22 # Real time elapsed on the host
|
||||
host_inst_rate 911205 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1604486 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 974425819 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 402856 # Number of bytes of host memory used
|
||||
host_seconds 173.38 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192463 # Number of ops (including micro ops) simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 717246011 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2458815323 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 90779446 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 308475610 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10308191240 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 4245314267 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14553505507 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10308191240 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10308191240 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1439319674 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1439319674 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10308191240 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5684633941 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 15992825181 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10308191209 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 4245314255 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14553505464 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10308191209 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10308191209 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1439319681 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1439319681 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10308191209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5684633936 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 15992825145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 337900079 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 337900080 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 157988548 # Number of instructions committed
|
||||
system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
|
||||
system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 278186171 # number of integer instructions
|
||||
system.cpu.num_int_insts 278186173 # number of integer instructions
|
||||
system.cpu.num_fp_insts 40 # number of float instructions
|
||||
system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 122219135 # number of memory refs
|
||||
system.cpu.num_mem_refs 122219136 # number of memory refs
|
||||
system.cpu.num_load_insts 90779384 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439751 # Number of store instructions
|
||||
system.cpu.num_store_insts 31439752 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 337900079 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 337900080 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -61,21 +61,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -99,21 +100,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 23:03:49
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:35:30
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -25,4 +25,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 368209206000 because target called exit()
|
||||
Exiting @ tick 365989064000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.365989 # Number of seconds simulated
|
||||
sim_ticks 365989063000 # Number of ticks simulated
|
||||
final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 365989064000 # Number of ticks simulated
|
||||
final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 621192 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1439024491 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 361884 # Number of bytes of host memory used
|
||||
host_seconds 254.33 # Real time elapsed on the host
|
||||
host_inst_rate 426513 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 751021 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 988040650 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 411308 # Number of bytes of host memory used
|
||||
host_seconds 370.42 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192463 # Number of ops (including micro ops) simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
|
||||
|
|
@ -35,35 +35,35 @@ system.physmem.bw_total::cpu.inst 140419 # To
|
|||
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 731978126 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 731978128 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 157988548 # Number of instructions committed
|
||||
system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
|
||||
system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 278186171 # number of integer instructions
|
||||
system.cpu.num_int_insts 278186173 # number of integer instructions
|
||||
system.cpu.num_fp_insts 40 # number of float instructions
|
||||
system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 122219135 # number of memory refs
|
||||
system.cpu.num_mem_refs 122219136 # number of memory refs
|
||||
system.cpu.num_load_insts 90779384 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439751 # Number of store instructions
|
||||
system.cpu.num_store_insts 31439752 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 731978126 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 731978128 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 665.632509 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 665.632509 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
|
||||
|
|
@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 120152368 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
|
||||
|
|
@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 28097140000
|
|||
system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
|
||||
|
|
@ -236,13 +236,13 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 318 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 20041.899874 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 19330.353270 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 557.646384 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 19330.353217 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 557.646383 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,7 +78,6 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -465,9 +464,6 @@ int_master=system.membus.slave[2]
|
|||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -528,9 +524,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/parser
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,28 +1,17 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 16:49:35
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 01:06:22
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *********info: Increasing stack size by one page.
|
||||
**************************************info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
**
|
||||
****************************************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
|
|
@ -34,8 +23,18 @@ Processing sentences in batch mode
|
|||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
|
|
@ -75,9 +74,11 @@ Echoing of input sentence turned on.
|
|||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 434496110500 because target called exit()
|
||||
Exiting @ tick 434474519000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
|
|
@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:29:08
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:35:29
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -71,4 +71,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 885229327000 because target called exit()
|
||||
Exiting @ tick 885229327500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,59 +1,59 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.885229 # Number of seconds simulated
|
||||
sim_ticks 885229327000 # Number of ticks simulated
|
||||
final_tick 885229327000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 885229327500 # Number of ticks simulated
|
||||
final_tick 885229327500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 957113 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1769809 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1024655834 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269560 # Number of bytes of host memory used
|
||||
host_seconds 863.93 # Real time elapsed on the host
|
||||
host_inst_rate 941243 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1740465 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1007666185 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271920 # Number of bytes of host memory used
|
||||
host_seconds 878.49 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988700 # Number of ops (including micro ops) simulated
|
||||
sim_ops 1528988701 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 2285655656 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10832432176 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 991849462 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 991849462 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 384102185 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1452449250 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 9654872765 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12236865460 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 9654872765 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 9654872765 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1120443516 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1120443516 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 9654872765 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_writes::cpu.data 149160202 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 149160202 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 9654872760 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2581992694 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12236865453 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 9654872760 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 9654872760 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1120443518 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1120443518 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 9654872760 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13357308977 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13357308971 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 1770458655 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1770458656 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826877110 # Number of instructions committed
|
||||
system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
|
||||
system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1528317558 # number of integer instructions
|
||||
system.cpu.num_int_insts 1528317560 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 533262341 # number of memory refs
|
||||
system.cpu.num_mem_refs 533262342 # number of memory refs
|
||||
system.cpu.num_load_insts 384102156 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.num_store_insts 149160186 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1770458655 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1770458656 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -61,21 +61,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -99,21 +100,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:29:27
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:51:49
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -71,4 +71,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 1652606827000 because target called exit()
|
||||
Exiting @ tick 1647872848000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.647873 # Number of seconds simulated
|
||||
sim_ticks 1647872847000 # Number of ticks simulated
|
||||
final_tick 1647872847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1647872848000 # Number of ticks simulated
|
||||
final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 897428 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1659445 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1788472844 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230968 # Number of bytes of host memory used
|
||||
host_seconds 921.39 # Real time elapsed on the host
|
||||
host_inst_rate 488671 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 903607 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 973865405 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280376 # Number of bytes of host memory used
|
||||
host_seconds 1692.10 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988700 # Number of ops (including micro ops) simulated
|
||||
sim_ops 1528988701 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory
|
||||
|
|
@ -33,37 +33,37 @@ system.physmem.bw_write::total 11351788 # Wr
|
|||
system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26154601 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3295745694 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3295745696 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826877110 # Number of instructions committed
|
||||
system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
|
||||
system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1528317558 # number of integer instructions
|
||||
system.cpu.num_int_insts 1528317560 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 533262341 # number of memory refs
|
||||
system.cpu.num_mem_refs 533262342 # number of memory refs
|
||||
system.cpu.num_load_insts 384102156 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.num_store_insts 149160186 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3295745694 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3295745696 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tagsinuse 881.356492 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 881.356492 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
|
||||
|
|
@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4086.415788 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.415788 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 530743928 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 530743929 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
|
||||
|
|
@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 48668884500
|
|||
system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
|
||||
|
|
@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 348459 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 29286.402699 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 755936429000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21041.299363 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.warmup_cycle 755936430000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21041.299350 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 8105.344817 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 8105.344812 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
|
|
@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:29:07
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:35:30
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -26,4 +26,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 2846007226500 because target called exit()
|
||||
Exiting @ tick 2846007227000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,59 +1,59 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.846007 # Number of seconds simulated
|
||||
sim_ticks 2846007226500 # Number of ticks simulated
|
||||
final_tick 2846007226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 2846007227000 # Number of ticks simulated
|
||||
final_tick 2846007227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1027178 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1600436 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 971834142 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265228 # Number of bytes of host memory used
|
||||
host_seconds 2928.49 # Real time elapsed on the host
|
||||
host_inst_rate 1003542 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1563610 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 949472024 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267592 # Number of bytes of host memory used
|
||||
host_seconds 2997.46 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862594 # Number of ops (including micro ops) simulated
|
||||
sim_ops 4686862595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5023868343 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 37129731399 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 1544656790 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 1544656790 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1239184745 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5252417627 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 438528337 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 438528337 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 11281019513 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 11281019511 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 13046253380 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 11281019513 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 11281019513 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 542745210 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 542745210 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 11281019513 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2307979077 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13588998590 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 13046253378 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 11281019511 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 11281019511 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 11281019511 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13588998589 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 5692014454 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5692014455 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 3008081022 # Number of instructions committed
|
||||
system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
|
||||
system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4686862523 # number of integer instructions
|
||||
system.cpu.num_int_insts 4686862525 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1677713082 # number of memory refs
|
||||
system.cpu.num_mem_refs 1677713083 # number of memory refs
|
||||
system.cpu.num_load_insts 1239184745 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528337 # Number of store instructions
|
||||
system.cpu.num_store_insts 438528338 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5692014454 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 5692014455 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -61,21 +61,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -99,21 +100,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -185,7 +188,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:29:08
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:38:11
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -26,4 +26,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 5901048883000 because target called exit()
|
||||
Exiting @ tick 5882580525000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.882581 # Number of seconds simulated
|
||||
sim_ticks 5882580524000 # Number of ticks simulated
|
||||
final_tick 5882580524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 5882580525000 # Number of ticks simulated
|
||||
final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 472403 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 736047 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 923827707 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227772 # Number of bytes of host memory used
|
||||
host_seconds 6367.62 # Real time elapsed on the host
|
||||
host_inst_rate 506721 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 789517 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 990939541 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 276172 # Number of bytes of host memory used
|
||||
host_seconds 5936.37 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862594 # Number of ops (including micro ops) simulated
|
||||
sim_ops 4686862595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
|
||||
|
|
@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 7344 # To
|
|||
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 11765161048 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 11765161050 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 3008081022 # Number of instructions committed
|
||||
system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
|
||||
system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4686862523 # number of integer instructions
|
||||
system.cpu.num_int_insts 4686862525 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1677713082 # number of memory refs
|
||||
system.cpu.num_mem_refs 1677713083 # number of memory refs
|
||||
system.cpu.num_load_insts 1239184745 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528337 # Number of store instructions
|
||||
system.cpu.num_store_insts 438528338 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11765161048 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 11765161050 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 10 # number of replacements
|
||||
|
|
@ -137,21 +137,21 @@ system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926
|
|||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 58853920000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
|
||||
|
|
@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 200710756000
|
|||
system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
|
||||
|
|
@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1926197 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 31136.249390 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 340768633000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15396.795539 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.warmup_cycle 340768634000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15396.795536 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15713.812836 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15713.812833 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,7 +78,6 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -465,9 +464,6 @@ int_master=system.membus.slave[2]
|
|||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -528,7 +524,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/twolf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,14 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 17:50:59
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:48:42
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -22,4 +26,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 82887492500 because target called exit()
|
||||
122 123 124 Exiting @ tick 82648140000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
|
|
@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atom
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:29:08
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 00:50:19
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
|
||||
|
|
@ -26,4 +26,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 131393067000 because target called exit()
|
||||
122 123 124 Exiting @ tick 131393067500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,59 +1,59 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.131393 # Number of seconds simulated
|
||||
sim_ticks 131393067000 # Number of ticks simulated
|
||||
final_tick 131393067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 131393067500 # Number of ticks simulated
|
||||
final_tick 131393067500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 917611 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1537997 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 912899116 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272856 # Number of bytes of host memory used
|
||||
host_seconds 143.93 # Real time elapsed on the host
|
||||
host_inst_rate 889897 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1491546 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 885328041 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275216 # Number of bytes of host memory used
|
||||
host_seconds 148.41 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221362961 # Number of ops (including micro ops) simulated
|
||||
sim_ops 221362962 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 310423750 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1698378686 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 99822189 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 99822189 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 56682004 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 230176371 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 20515730 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 20515730 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10563380304 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2362558064 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12925938368 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10563380304 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10563380304 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 759721889 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 759721889 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10563380304 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3122279953 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13685660256 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10563380264 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2362558055 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12925938319 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10563380264 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10563380264 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 759721901 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 759721901 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10563380264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3122279956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13685660219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 262786135 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 262786136 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 132071193 # Number of instructions committed
|
||||
system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses
|
||||
system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 220339550 # number of integer instructions
|
||||
system.cpu.num_int_insts 220339552 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2162459 # number of float instructions
|
||||
system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 77165302 # number of memory refs
|
||||
system.cpu.num_mem_refs 77165303 # number of memory refs
|
||||
system.cpu.num_load_insts 56649586 # Number of load instructions
|
||||
system.cpu.num_store_insts 20515716 # Number of store instructions
|
||||
system.cpu.num_store_insts 20515717 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 262786135 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 262786136 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -61,21 +61,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -99,21 +100,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 22:29:00
|
||||
gem5 started Sep 10 2012 22:57:57
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 01:16:52
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
|
||||
|
|
@ -26,4 +26,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 250980994000 because target called exit()
|
||||
122 123 124 Exiting @ tick 250953956000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.250954 # Number of seconds simulated
|
||||
sim_ticks 250953955000 # Number of ticks simulated
|
||||
final_tick 250953955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 250953956000 # Number of ticks simulated
|
||||
final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 366685 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 614596 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 696753053 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236244 # Number of bytes of host memory used
|
||||
host_seconds 360.18 # Real time elapsed on the host
|
||||
host_inst_rate 472281 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 791585 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 897401473 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 283668 # Number of bytes of host memory used
|
||||
host_seconds 279.65 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221362961 # Number of ops (including micro ops) simulated
|
||||
sim_ops 221362962 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
|
||||
|
|
@ -28,35 +28,35 @@ system.physmem.bw_total::cpu.inst 724276 # To
|
|||
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 501907910 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 501907912 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 132071193 # Number of instructions committed
|
||||
system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses
|
||||
system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 220339550 # number of integer instructions
|
||||
system.cpu.num_int_insts 220339552 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2162459 # number of float instructions
|
||||
system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 77165302 # number of memory refs
|
||||
system.cpu.num_mem_refs 77165303 # number of memory refs
|
||||
system.cpu.num_load_insts 56649586 # Number of load instructions
|
||||
system.cpu.num_store_insts 20515716 # Number of store instructions
|
||||
system.cpu.num_store_insts 20515717 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 501907910 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 501907912 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1455.296654 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1455.296648 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1455.296654 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1455.296648 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
|
||||
|
|
@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1363.457581 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 77195829 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40522.744882 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1363.457581 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 77195829 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 77195829 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 77195829 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 77195829 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 77195830 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
|
||||
|
|
@ -163,12 +163,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 104356500
|
|||
system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 77197734 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 77197734 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 77197734 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 77197734 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
|
||||
|
|
@ -229,14 +229,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2058.178702 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1829.978594 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 228.178364 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1829.978587 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 228.178363 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -78,7 +78,6 @@ iewToFetchDelay=1
|
|||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -465,9 +464,6 @@ int_master=system.membus.slave[2]
|
|||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -528,7 +524,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/test-progs/hello/bin/x86/linux/hello
|
||||
executable=tests/test-progs/hello/bin/x86/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 30 2012 11:14:29
|
||||
gem5 started Oct 30 2012 16:15:47
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 01:12:54
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@ sim_seconds 0.000015 # Nu
|
|||
sim_ticks 15014000 # Number of ticks simulated
|
||||
final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 32657 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 59148 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 91121721 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223384 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 27939 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 50607 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 77954156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273052 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9745 # Number of ops (including micro ops) simulated
|
||||
sim_ops 9746 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
|
||||
|
|
@ -210,16 +210,16 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 18 #
|
|||
system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.378572 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.879282 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 175 0.94% 84.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 261 1.40% 85.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 171 0.92% 84.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 265 1.43% 85.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -233,44 +233,44 @@ system.cpu.decode.BlockedCycles 3616 # Nu
|
|||
system.cpu.decode.RunCycles 3547 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 24449 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 24452 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 3325 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 22967 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 22970 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 25104 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 55188 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 55172 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 25107 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 55203 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 55187 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 14044 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 14046 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1755 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1757 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 20454 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 17349 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsAdded 20458 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 17350 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 9974 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 13873 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedInstsExamined 9975 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 13877 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.933595 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.794406 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.933649 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.794423 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1386 7.46% 78.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1042 5.61% 84.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1385 7.45% 78.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1043 5.61% 84.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle
|
||||
|
|
@ -315,8 +315,8 @@ system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # at
|
|||
system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 13962 80.48% 80.51% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 13964 80.48% 80.51% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued
|
||||
|
|
@ -345,28 +345,28 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1900 10.95% 91.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1482 8.54% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1899 10.95% 91.45% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1483 8.55% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 17349 # Type of FU issued
|
||||
system.cpu.iq.rate 0.577742 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 17350 # Type of FU issued
|
||||
system.cpu.iq.rate 0.577775 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010260 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 53664 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 30472 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 16003 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.010259 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 53666 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 30475 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 16004 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 17518 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 17520 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.forwLoads 158 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
|
|
@ -375,44 +375,44 @@ system.cpu.iew.iewIdleCycles 0 # Nu
|
|||
system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 20491 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 20493 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1755 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1757 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 16425 # Number of executed instructions
|
||||
system.cpu.iew.iewExecutedInsts 16426 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3140 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs 3141 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1630 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1363 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.546971 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 16197 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 16007 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 10178 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 15727 # num instructions consuming a value
|
||||
system.cpu.iew.exec_stores 1364 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.547005 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 16198 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 16008 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 10179 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 15729 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.533051 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.647167 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.533085 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.647149 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 10745 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 10746 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.581687 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.458321 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.581747 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.458276 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 13226 78.95% 78.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1316 7.86% 86.80% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 596 3.56% 90.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 13224 78.94% 78.94% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1319 7.87% 86.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 595 3.55% 90.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle
|
||||
|
|
@ -424,32 +424,32 @@ system.cpu.commit.committed_per_cycle::min_value 0
|
|||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 5380 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 1986 # Number of memory references committed
|
||||
system.cpu.commit.refs 1987 # Number of memory references committed
|
||||
system.cpu.commit.loads 1052 # Number of loads committed
|
||||
system.cpu.commit.membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.branches 1208 # Number of branches committed
|
||||
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
|
||||
system.cpu.commit.int_insts 9652 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 37022 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 42839 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 37024 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 42843 # The number of ROB writes
|
||||
system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 5380 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
|
||||
system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 28874 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 17232 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 28877 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 17233 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 7155 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 7157 # number of misc regfile reads
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1482 # Total number of references to valid blocks.
|
||||
|
|
@ -534,6 +534,110 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2284 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 202 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
|
|
@ -659,109 +763,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2284 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 202 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081186 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.081186 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045747 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045747 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
|
|
@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 21:50:34
|
||||
gem5 started Sep 10 2012 21:50:39
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 01:20:22
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 5614000 because target called exit()
|
||||
Exiting @ tick 5614500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,59 +1,59 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000006 # Number of seconds simulated
|
||||
sim_ticks 5614000 # Number of ticks simulated
|
||||
final_tick 5614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 5614500 # Number of ticks simulated
|
||||
final_tick 5614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 59958 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 108572 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 62528382 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261084 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 95396 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 172737 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 99466308 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263448 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9746 # Number of ops (including micro ops) simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 61976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7110 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7112 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 934 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 9781261133 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1258282864 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 11039543997 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 9781261133 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 9781261133 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1266476665 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1266476665 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 9781261133 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2524759530 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12306020663 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 935 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 9780390061 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1258170808 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 11038560869 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 9780390061 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 9780390061 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1266720100 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1266720100 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 9780390061 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2524890907 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12305280969 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 11229 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 11230 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
system.cpu.committedOps 9746 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses
|
||||
system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9651 # number of integer instructions
|
||||
system.cpu.num_int_insts 9653 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1986 # number of memory refs
|
||||
system.cpu.num_mem_refs 1987 # number of memory refs
|
||||
system.cpu.num_load_insts 1052 # Number of load instructions
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.num_store_insts 935 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11229 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 11230 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ version=0
|
|||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
numa_high_bit=5
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Sep/10/2012 21:50:40
|
||||
Real time: Dec/30/2012 01:12:43
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.48
|
||||
Virtual_time_in_minutes: 0.008
|
||||
Virtual_time_in_hours: 0.000133333
|
||||
Virtual_time_in_days: 5.55556e-06
|
||||
Virtual_time_in_seconds: 0.51
|
||||
Virtual_time_in_minutes: 0.0085
|
||||
Virtual_time_in_hours: 0.000141667
|
||||
Virtual_time_in_days: 5.90278e-06
|
||||
|
||||
Ruby_current_time: 121759
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 121759
|
||||
|
||||
mbytes_resident: 57.9453
|
||||
mbytes_total: 275.082
|
||||
resident_ratio: 0.210662
|
||||
mbytes_resident: 60.1836
|
||||
mbytes_total: 277.391
|
||||
resident_ratio: 0.217006
|
||||
|
||||
ruby_cycles_executed: [ 121760 ]
|
||||
|
||||
|
|
@ -29,17 +29,17 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8851 average: 1 | standard deviation: 0 | 0 8851 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8852 average: 1 | standard deviation: 0 | 0 8852 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 1 max: 125 count: 8850 average: 12.7581 | standard deviation: 22.8706 | 0 0 0 7473 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 314 433 491 10 7 5 9 5 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 2 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency: [binsize: 1 max: 125 count: 8851 average: 12.7565 | standard deviation: 22.8681 | 0 0 0 7474 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 1 max: 101 count: 1044 average: 33.113 | standard deviation: 31.8551 | 0 0 0 545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 1 max: 92 count: 934 average: 20.1188 | standard deviation: 28.2308 | 0 0 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 2 3 9 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66288 | standard deviation: 18.0056 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 158 170 234 6 4 3 7 4 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0877 | standard deviation: 28.194 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66404 | standard deviation: 18.01 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_RMW_Read: [binsize: 1 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 7473 average: 3 | standard deviation: 0 | 0 0 0 7473 ]
|
||||
miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7153 | standard deviation: 6.33839 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 314 433 491 10 7 5 9 5 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 2 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 7474 average: 3 | standard deviation: 0 | 0 0 0 7474 ]
|
||||
miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7124 | standard deviation: 6.32886 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -52,10 +52,10 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 aver
|
|||
imcomplete_dir_Times: 1376
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 545 average: 3 | standard deviation: 0 | 0 0 0 545 ]
|
||||
miss_latency_LD_Directory: [binsize: 1 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ]
|
||||
miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9488 | standard deviation: 6.5357 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 2 3 9 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 681 average: 3 | standard deviation: 0 | 0 0 0 681 ]
|
||||
miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9016 | standard deviation: 6.43269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6241 average: 3 | standard deviation: 0 | 0 0 0 6241 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.3917 | standard deviation: 5.66183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 158 170 234 6 4 3 7 4 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4045 | standard deviation: 5.68761 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
|
||||
miss_latency_RMW_Read_Directory: [binsize: 1 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
|
|
@ -89,10 +89,10 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11940
|
||||
page_faults: 0
|
||||
page_reclaims: 12527
|
||||
page_faults: 3
|
||||
swaps: 0
|
||||
block_inputs: 24
|
||||
block_inputs: 1360
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
|
|
@ -154,7 +154,7 @@ Cache Stats: system.l1_cntrl0.cacheMemory
|
|||
- Event Counts -
|
||||
Load [1044 ] 1044
|
||||
Ifetch [6864 ] 6864
|
||||
Store [942 ] 942
|
||||
Store [943 ] 943
|
||||
Data [1377 ] 1377
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
|
|
@ -173,7 +173,7 @@ II Writeback_Nack [0 ] 0
|
|||
|
||||
M Load [545 ] 545
|
||||
M Ifetch [6241 ] 6241
|
||||
M Store [687 ] 687
|
||||
M Store [688 ] 688
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [1373 ] 1373
|
||||
|
|
@ -194,16 +194,16 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_reads: 1377
|
||||
memory_writes: 1373
|
||||
memory_refreshes: 846
|
||||
memory_total_request_delays: 1965
|
||||
memory_delays_per_request: 0.714545
|
||||
memory_total_request_delays: 1964
|
||||
memory_delays_per_request: 0.714182
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1962
|
||||
memory_stalls_for_bank_busy: 830
|
||||
memory_delays_behind_head_of_bank_queue: 4
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1960
|
||||
memory_stalls_for_bank_busy: 826
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 62
|
||||
memory_stalls_for_bus: 1039
|
||||
memory_stalls_for_bus: 1041
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 31
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 21:50:34
|
||||
gem5 started Sep 10 2012 21:50:39
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 01:12:43
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -4,35 +4,35 @@ sim_seconds 0.000122 # Nu
|
|||
sim_ticks 121759 # Number of ticks simulated
|
||||
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 21174 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38347 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 479042 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 281688 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
host_inst_rate 28531 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51675 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 645460 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 284052 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9746 # Number of ops (including micro ops) simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 61976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7110 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7112 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 934 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 935 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 450989249 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 58016245 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 509005494 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 450989249 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 450989249 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 58394041 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 58394041 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 58410467 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 58410467 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 450989249 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 116410286 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 567399535 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 116426712 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 567415961 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -44,20 +44,20 @@ system.cpu.numCycles 121759 # nu
|
|||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
system.cpu.committedOps 9746 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses
|
||||
system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9651 # number of integer instructions
|
||||
system.cpu.num_int_insts 9653 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1986 # number of memory refs
|
||||
system.cpu.num_mem_refs 1987 # number of memory refs
|
||||
system.cpu.num_load_insts 1052 # Number of load instructions
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.num_store_insts 935 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 121759 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -61,22 +61,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -91,7 +91,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -100,22 +100,22 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=1000
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=1000
|
||||
response_latency=2
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -124,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
|
|||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=1
|
||||
clock=500
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -141,31 +141,31 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=1
|
||||
clock=500
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=10000
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=10000
|
||||
response_latency=20
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
|
@ -175,10 +175,10 @@ mem_side=system.membus.slave[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
|
|
@ -217,7 +217,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 10 2012 21:50:34
|
||||
gem5 started Sep 10 2012 21:50:39
|
||||
gem5 compiled Dec 30 2012 00:35:18
|
||||
gem5 started Dec 30 2012 01:20:12
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 29676000 because target called exit()
|
||||
Exiting @ tick 28357000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 28356000 # Number of ticks simulated
|
||||
final_tick 28356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 28357000 # Number of ticks simulated
|
||||
final_tick 28357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 134366 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 243261 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 707485860 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226568 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 86866 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 157296 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 457476490 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271900 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9746 # Number of ops (including micro ops) simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
|
||||
|
|
@ -19,46 +19,46 @@ system.physmem.bytes_inst_read::total 14528 # Nu
|
|||
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 512343067 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 302440401 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 814783467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 512343067 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 512343067 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 512343067 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 302440401 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 814783467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 512324999 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 302429735 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 814754734 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 512324999 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 512324999 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 512324999 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 302429735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 814754734 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 56712 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 56714 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
system.cpu.committedOps 9746 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses
|
||||
system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9651 # number of integer instructions
|
||||
system.cpu.num_int_insts 9653 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1986 # number of memory refs
|
||||
system.cpu.num_mem_refs 1987 # number of memory refs
|
||||
system.cpu.num_load_insts 1052 # Number of load instructions
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.num_store_insts 935 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 56712 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 56714 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 105.556077 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 105.553131 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 105.556077 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.051541 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.051541 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 105.553131 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.051540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.051540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
|
||||
|
|
@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 80.800961 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1852 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13.820896 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 80.800961 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.019727 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.019727 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1852 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1852 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1852 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1852 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1853 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
|
||||
|
|
@ -163,20 +163,20 @@ system.cpu.dcache.overall_miss_latency::cpu.data 7370000
|
|||
system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1986 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 1986 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1986 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 1986 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.067472 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.067472 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.067472 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.067472 # miss rate for overall accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
|
|
@ -211,12 +211,12 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000
|
|||
system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084582 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.067472 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.067472 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
||||
|
|
@ -227,14 +227,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 134.040949 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 134.037527 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 105.564188 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 28.476761 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 105.561241 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 28.476285 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004091 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
|
|
|
|||
Loading…
Reference in a new issue