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Uart fix.

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dev/uart8250.cc:
    Fixed implementation of "transmit interrupt clear".

--HG--
extra : convert_revision : cb69d61413ea799d5d3825fe2f0891dd72995561
This commit is contained in:
Miguel Serrano 2005-08-16 15:44:57 -04:00
parent b64eae5e52
commit 1906abcde0
1 changed files with 6 additions and 4 deletions
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10
dev/uart8250.cc
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@ -147,13 +147,15 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
case 0x2: // Intr Identification Register (IIR) case 0x2: // Intr Identification Register (IIR)
DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status); DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
//Tx interrupts are cleared on IIR reads if (status & RX_INT) /* Rx data interrupt has a higher priority */
status &= ~TX_INT;
if (status & RX_INT)
*(uint8_t*)data = IIR_RXID; *(uint8_t*)data = IIR_RXID;
else if (status & TX_INT)
*(uint8_t*)data = IIR_TXID;
else else
*(uint8_t*)data = IIR_NOPEND; *(uint8_t*)data = IIR_NOPEND;
//Tx interrupts are cleared on IIR reads
status &= ~TX_INT;
break; break;
case 0x3: // Line Control Register (LCR) case 0x3: // Line Control Register (LCR)
*(uint8_t*)data = LCR; *(uint8_t*)data = LCR;