tests: Add a memtest version using the ideal SnoopFilter
This patch adds a basic regression test for the snoop filter. --HG-- rename : tests/configs/memtest.py => tests/configs/memtest-filter.py
This commit is contained in:
Andreas Hansson
parent
435f4aec3d
commit
1884bcc03b
6 changed files with 2529 additions and 1 deletions
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@ -344,7 +344,7 @@ configs += ['simple-atomic', 'simple-atomic-mp',
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'inorder-timing',
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'minor-timing', 'minor-timing-mp',
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'o3-timing', 'o3-timing-mp',
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'rubytest', 'memtest',
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'rubytest', 'memtest', 'memtest-filter',
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'tgen-simple-mem', 'tgen-dram-ctrl']
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if env['PROTOCOL'] != 'None':
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87
tests/configs/memtest-filter.py
Normal file
87
tests/configs/memtest-filter.py
Normal file
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@ -0,0 +1,87 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Caches import *
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#MAX CORES IS 8 with the fals sharing method
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nb_cores = 8
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cpus = [ MemTest() for i in xrange(nb_cores) ]
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# system simulated
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system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
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funcbus = NoncoherentBus(),
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physmem = SimpleMemory(),
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membus = CoherentBus(width=16, snoop_filter = SnoopFilter()))
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# Dummy voltage domain for all our clock domains
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system.voltage_domain = VoltageDomain()
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system.clk_domain = SrcClockDomain(clock = '1GHz',
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voltage_domain = system.voltage_domain)
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# Create a seperate clock domain for components that should run at
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# CPUs frequency
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system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
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voltage_domain = system.voltage_domain)
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system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16,
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snoop_filter = SnoopFilter())
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system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.master
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# connect l2c to membus
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system.l2c.mem_side = system.membus.slave
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# add L1 caches
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for cpu in cpus:
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# All cpus are associated with cpu_clk_domain
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cpu.clk_domain = system.cpu_clk_domain
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cpu.l1c = L1Cache(size = '32kB', assoc = 4)
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cpu.l1c.cpu_side = cpu.test
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cpu.l1c.mem_side = system.toL2Bus.slave
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system.funcbus.slave = cpu.functional
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system.system_port = system.membus.slave
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# connect reference memory to funcbus
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system.funcmem.port = system.funcbus.master
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# connect memory to membus
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system.physmem.port = system.membus.master
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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#root.trace.flags="Cache CachePort MemoryAccess"
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#root.trace.cycle=1
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@ -0,0 +1,610 @@
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[root]
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type=Root
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children=system
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eventq_index=0
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full_system=false
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=timing
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mem_ranges=
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memories=system.physmem system.funcmem
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num_work_ids=16
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[1]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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eventq_index=0
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voltage_domain=system.voltage_domain
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[system.cpu0]
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type=MemTest
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children=l1c
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atomic=false
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[0]
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test=system.cpu0.l1c.cpu_side
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[system.cpu0.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu0.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.test
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mem_side=system.toL2Bus.slave[0]
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[system.cpu0.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu1]
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type=MemTest
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children=l1c
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atomic=false
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[1]
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test=system.cpu1.l1c.cpu_side
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[system.cpu1.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu1.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.test
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mem_side=system.toL2Bus.slave[1]
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[system.cpu1.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu2]
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type=MemTest
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children=l1c
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atomic=false
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[2]
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test=system.cpu2.l1c.cpu_side
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[system.cpu2.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu2.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu2.test
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mem_side=system.toL2Bus.slave[2]
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[system.cpu2.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu3]
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type=MemTest
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children=l1c
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atomic=false
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[3]
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test=system.cpu3.l1c.cpu_side
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[system.cpu3.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu3.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu3.test
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mem_side=system.toL2Bus.slave[3]
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[system.cpu3.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu4]
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type=MemTest
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children=l1c
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atomic=false
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[4]
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test=system.cpu4.l1c.cpu_side
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[system.cpu4.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu4.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu4.test
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mem_side=system.toL2Bus.slave[4]
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[system.cpu4.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu5]
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type=MemTest
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children=l1c
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atomic=false
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[5]
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test=system.cpu5.l1c.cpu_side
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[system.cpu5.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu5.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu5.test
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mem_side=system.toL2Bus.slave[5]
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[system.cpu5.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu6]
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type=MemTest
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children=l1c
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atomic=false
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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issue_dmas=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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suppress_func_warnings=false
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sys=system
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trace_addr=0
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functional=system.funcbus.slave[6]
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test=system.cpu6.l1c.cpu_side
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|
||||
[system.cpu6.l1c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu6.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu6.test
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu6.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_source_unaligned=50
|
||||
percent_uncacheable=10
|
||||
progress_interval=10000
|
||||
suppress_func_warnings=false
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcbus.slave[7]
|
||||
test=system.cpu7.l1c.cpu_side
|
||||
|
||||
[system.cpu7.l1c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu7.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu7.test
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu7.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.funcbus]
|
||||
type=NoncoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.funcmem.port
|
||||
slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=false
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
port=system.funcbus.master[0]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=65536
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=65536
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.l2c.mem_side system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=3
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
snoop_filter=system.toL2Bus.snoop_filter
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
|
||||
|
||||
[system.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=3
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
74
tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
Executable file
74
tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
Executable file
|
|
@ -0,0 +1,74 @@
|
|||
warn: failed to generate dot output from build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/config.dot
|
||||
system.cpu6: completed 10000 read, 5415 write accesses @145109000
|
||||
system.cpu2: completed 10000 read, 5349 write accesses @145417500
|
||||
system.cpu1: completed 10000 read, 5329 write accesses @146140000
|
||||
system.cpu0: completed 10000 read, 5371 write accesses @146497000
|
||||
system.cpu4: completed 10000 read, 5466 write accesses @147507000
|
||||
system.cpu3: completed 10000 read, 5586 write accesses @147982000
|
||||
system.cpu5: completed 10000 read, 5427 write accesses @148047500
|
||||
system.cpu7: completed 10000 read, 5356 write accesses @148467500
|
||||
system.cpu6: completed 20000 read, 10673 write accesses @289538000
|
||||
system.cpu2: completed 20000 read, 10526 write accesses @290832000
|
||||
system.cpu1: completed 20000 read, 10766 write accesses @292890999
|
||||
system.cpu5: completed 20000 read, 10736 write accesses @293627000
|
||||
system.cpu7: completed 20000 read, 10730 write accesses @293693000
|
||||
system.cpu0: completed 20000 read, 10671 write accesses @294206500
|
||||
system.cpu4: completed 20000 read, 10944 write accesses @296769500
|
||||
system.cpu3: completed 20000 read, 10962 write accesses @297951000
|
||||
system.cpu2: completed 30000 read, 15840 write accesses @436954000
|
||||
system.cpu1: completed 30000 read, 16134 write accesses @439432500
|
||||
system.cpu6: completed 30000 read, 16128 write accesses @439710500
|
||||
system.cpu7: completed 30000 read, 16048 write accesses @440819000
|
||||
system.cpu5: completed 30000 read, 16126 write accesses @441698000
|
||||
system.cpu3: completed 30000 read, 16409 write accesses @444974000
|
||||
system.cpu4: completed 30000 read, 16439 write accesses @445869500
|
||||
system.cpu0: completed 30000 read, 16254 write accesses @446194000
|
||||
system.cpu2: completed 40000 read, 21231 write accesses @582932500
|
||||
system.cpu6: completed 40000 read, 21466 write accesses @586141500
|
||||
system.cpu1: completed 40000 read, 21414 write accesses @588066500
|
||||
system.cpu3: completed 40000 read, 21735 write accesses @588220000
|
||||
system.cpu5: completed 40000 read, 21572 write accesses @588767000
|
||||
system.cpu7: completed 40000 read, 21513 write accesses @590091000
|
||||
system.cpu0: completed 40000 read, 21682 write accesses @592843000
|
||||
system.cpu4: completed 40000 read, 21885 write accesses @593488000
|
||||
system.cpu2: completed 50000 read, 26639 write accesses @730512000
|
||||
system.cpu3: completed 50000 read, 26953 write accesses @733051500
|
||||
system.cpu6: completed 50000 read, 26889 write accesses @736295000
|
||||
system.cpu1: completed 50000 read, 26860 write accesses @736946500
|
||||
system.cpu4: completed 50000 read, 27157 write accesses @739104500
|
||||
system.cpu5: completed 50000 read, 27043 write accesses @739175000
|
||||
system.cpu7: completed 50000 read, 27030 write accesses @739274500
|
||||
system.cpu0: completed 50000 read, 27007 write accesses @740081999
|
||||
system.cpu2: completed 60000 read, 31935 write accesses @875520000
|
||||
system.cpu3: completed 60000 read, 32327 write accesses @878608000
|
||||
system.cpu1: completed 60000 read, 32037 write accesses @880758000
|
||||
system.cpu5: completed 60000 read, 32374 write accesses @883996500
|
||||
system.cpu4: completed 60000 read, 32578 write accesses @885209000
|
||||
system.cpu6: completed 60000 read, 32302 write accesses @886481999
|
||||
system.cpu0: completed 60000 read, 32356 write accesses @886645000
|
||||
system.cpu7: completed 60000 read, 32534 write accesses @888148500
|
||||
system.cpu3: completed 70000 read, 37577 write accesses @1026143000
|
||||
system.cpu2: completed 70000 read, 37542 write accesses @1027029999
|
||||
system.cpu1: completed 70000 read, 37457 write accesses @1029024000
|
||||
system.cpu5: completed 70000 read, 37722 write accesses @1029495500
|
||||
system.cpu6: completed 70000 read, 37640 write accesses @1032918500
|
||||
system.cpu0: completed 70000 read, 37692 write accesses @1034293500
|
||||
system.cpu7: completed 70000 read, 37955 write accesses @1034390500
|
||||
system.cpu4: completed 70000 read, 38136 write accesses @1036569000
|
||||
system.cpu3: completed 80000 read, 42898 write accesses @1173212500
|
||||
system.cpu2: completed 80000 read, 42932 write accesses @1173575000
|
||||
system.cpu1: completed 80000 read, 42886 write accesses @1177639500
|
||||
system.cpu5: completed 80000 read, 43232 write accesses @1178175000
|
||||
system.cpu0: completed 80000 read, 42958 write accesses @1178771500
|
||||
system.cpu6: completed 80000 read, 42919 write accesses @1180797000
|
||||
system.cpu7: completed 80000 read, 43430 write accesses @1183823000
|
||||
system.cpu4: completed 80000 read, 43550 write accesses @1185935999
|
||||
system.cpu2: completed 90000 read, 48239 write accesses @1319473000
|
||||
system.cpu3: completed 90000 read, 48329 write accesses @1322081500
|
||||
system.cpu1: completed 90000 read, 48223 write accesses @1323240500
|
||||
system.cpu5: completed 90000 read, 48632 write accesses @1326787000
|
||||
system.cpu0: completed 90000 read, 48351 write accesses @1327807500
|
||||
system.cpu6: completed 90000 read, 48287 write accesses @1329208000
|
||||
system.cpu7: completed 90000 read, 48796 write accesses @1329462500
|
||||
system.cpu4: completed 90000 read, 48969 write accesses @1334198500
|
||||
system.cpu2: completed 100000 read, 53603 write accesses @1466014000
|
||||
10
tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout
Executable file
10
tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout
Executable file
|
|
@ -0,0 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 28 2014 18:29:12
|
||||
gem5 started Feb 28 2014 18:30:27
|
||||
gem5 executing on cz310588hp
|
||||
command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1466014000 because maximum number of loads reached
|
||||
1747
tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
Normal file
1747
tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue