Fix for fetch to use the icache's block size to generate proper access size.
--HG-- extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
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@ -151,36 +151,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
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" RoundRobin,LSQcount,IQcount}\n");
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" RoundRobin,LSQcount,IQcount}\n");
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}
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}
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// Size of cache block.
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cacheBlkSize = 64;
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// Create mask to get rid of offset bits.
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cacheBlkMask = (cacheBlkSize - 1);
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for (int tid=0; tid < numThreads; tid++) {
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fetchStatus[tid] = Running;
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priorityList.push_back(tid);
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memReq[tid] = NULL;
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// Create space to store a cache line.
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cacheData[tid] = new uint8_t[cacheBlkSize];
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cacheDataPC[tid] = 0;
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cacheDataValid[tid] = false;
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delaySlotInfo[tid].branchSeqNum = -1;
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delaySlotInfo[tid].numInsts = 0;
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delaySlotInfo[tid].targetAddr = 0;
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delaySlotInfo[tid].targetReady = false;
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stalls[tid].decode = false;
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stalls[tid].rename = false;
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stalls[tid].iew = false;
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stalls[tid].commit = false;
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}
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// Get the size of an instruction.
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// Get the size of an instruction.
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instSize = sizeof(TheISA::MachInst);
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instSize = sizeof(TheISA::MachInst);
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}
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}
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@ -353,6 +323,36 @@ DefaultFetch<Impl>::initStage()
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nextNPC[tid] = cpu->readNextNPC(tid);
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nextNPC[tid] = cpu->readNextNPC(tid);
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#endif
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#endif
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}
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}
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// Size of cache block.
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cacheBlkSize = icachePort->peerBlockSize();
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// Create mask to get rid of offset bits.
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cacheBlkMask = (cacheBlkSize - 1);
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for (int tid=0; tid < numThreads; tid++) {
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fetchStatus[tid] = Running;
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priorityList.push_back(tid);
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memReq[tid] = NULL;
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// Create space to store a cache line.
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cacheData[tid] = new uint8_t[cacheBlkSize];
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cacheDataPC[tid] = 0;
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cacheDataValid[tid] = false;
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delaySlotInfo[tid].branchSeqNum = -1;
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delaySlotInfo[tid].numInsts = 0;
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delaySlotInfo[tid].targetAddr = 0;
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delaySlotInfo[tid].targetReady = false;
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stalls[tid].decode = false;
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stalls[tid].rename = false;
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stalls[tid].iew = false;
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stalls[tid].commit = false;
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}
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}
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}
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template<class Impl>
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template<class Impl>
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