ruby: x86 fs config support
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1b54344aeb
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2 changed files with 57 additions and 21 deletions
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@ -10,6 +10,7 @@
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# unmodified and in its entirety in all distributions of the software,
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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# modified or unmodified, in source code or in binary form.
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#
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#
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# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# All rights reserved.
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# All rights reserved.
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#
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#
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@ -286,7 +287,34 @@ def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port;
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return IO_address_space_base + port;
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def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
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def connectX86ClassicSystem(x86_sys):
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x86_sys.membus = MemBus(bus_id=1)
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x86_sys.physmem.port = x86_sys.membus.port
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# North Bridge
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x86_sys.iobus = Bus(bus_id=0)
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x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
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x86_sys.bridge.side_a = x86_sys.iobus.port
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x86_sys.bridge.side_b = x86_sys.membus.port
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# connect the io bus
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x86_sys.pc.attachIO(x86_sys.iobus)
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def connectX86RubySystem(x86_sys):
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# North Bridge
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x86_sys.piobus = Bus(bus_id=0)
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#
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# Pio functional accesses from devices need direct access to memory
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# RubyPort currently does support functional accesses. Therefore provide
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# the piobus a direct connection to physical memory
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#
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x86_sys.piobus.port = x86_sys.physmem.port
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x86_sys.pc.attachIO(x86_sys.piobus)
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def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
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if self == None:
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if self == None:
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self = X86System()
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self = X86System()
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@ -298,19 +326,16 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
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self.mem_mode = mem_mode
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self.mem_mode = mem_mode
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# Physical memory
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# Physical memory
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self.membus = MemBus(bus_id=1)
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.physmem.port = self.membus.port
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# North Bridge
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self.iobus = Bus(bus_id=0)
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self.bridge = Bridge(delay='50ns', nack_delay='4ns')
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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# Platform
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# Platform
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self.pc = Pc()
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self.pc = Pc()
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self.pc.attachIO(self.iobus)
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# Create and connect the busses required by each memory system
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if Ruby:
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connectX86RubySystem(self)
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else:
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connectX86ClassicSystem(self)
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self.intrctrl = IntrControl()
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self.intrctrl = IntrControl()
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@ -380,12 +405,11 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
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for i in range(3, 15):
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for i in range(3, 15):
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assignISAInt(i, i)
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assignISAInt(i, i)
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def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
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def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
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self = LinuxX86System()
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self = LinuxX86System()
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# Build up a generic x86 system and then specialize it for Linux
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# Build up the x86 system and then specialize it for Linux
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makeX86System(mem_mode, numCPUs, mdesc, self)
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makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
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# We assume below that there's at least 1MB of memory. We'll require 2
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# We assume below that there's at least 1MB of memory. We'll require 2
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# just to avoid corner cases.
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# just to avoid corner cases.
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@ -1,4 +1,4 @@
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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@ -109,12 +109,19 @@ FutureClass = None
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CPUClass.clock = options.clock
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CPUClass.clock = options.clock
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system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
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if buildEnv['TARGET_ISA'] == "alpha":
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system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
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system.ruby = Ruby.create_system(options,
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system.ruby = Ruby.create_system(options,
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system,
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system,
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system.piobus,
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system.piobus,
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system._dma_devices)
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system.dma_devices)
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elif buildEnv['TARGET_ISA'] == "x86":
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system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
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system.ruby = Ruby.create_system(options,
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system,
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system.piobus)
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else:
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fatal("incapable of building non-alpha or non-x86 full system!")
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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@ -124,6 +131,11 @@ for (i, cpu) in enumerate(system.cpu):
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#
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#
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cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
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cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
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cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
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cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
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if buildEnv['TARGET_ISA'] == "x86":
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cpu.itb.walker.port = system.ruby.cpu_ruby_ports[i].port
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cpu.dtb.walker.port = system.ruby.cpu_ruby_ports[i].port
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cpu.interrupts.pio = system.piobus.port
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cpu.interrupts.int_port = system.piobus.port
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root = Root(system = system)
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root = Root(system = system)
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