From 178d114fa5ed5927a2665a30ae5813ea2e2fbfea Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Sat, 7 Oct 2006 11:36:55 -0400
Subject: [PATCH] Fix infinite writebacks bug in cache.

src/mem/cache/cache_impl.hh:
    Make sure to pop the list.  Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
    Add an assert as sanity check in case .full() stops working again.

--HG--
extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311
---
 src/mem/cache/cache_impl.hh      | 1 +
 src/mem/cache/miss/mshr_queue.cc | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 00fecc2b7..46f4b0ebe 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -326,6 +326,7 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
                                    writebacks, pkt);
             while (!writebacks.empty()) {
                     missQueue->doWriteback(writebacks.front());
+                    writebacks.pop_front();
             }
         }
         missQueue->handleResponse(pkt, curTick + hitLatency);
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index e54f7aa08..bd9667529 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -128,6 +128,7 @@ MSHR*
 MSHRQueue::allocate(Packet * &pkt, int size)
 {
     Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1);
+    assert(!freeList.empty());
     MSHR *mshr = freeList.front();
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();