config: Add --memchecker option

This patch adds the --memchecker option, to denote that a MemChecker
should be instantiated for the system. The exact usage of the MemChecker
depends on the system configuration.

For now CacheConfig.py makes use of the option, adding MemCheckerMonitor
instances between CPUs and D-Caches.

Note, however, that currently this only provides limited checking on a
running system; other parts of the system, such as I/O devices are not
monitored, and may cause warnings to be issued by the monitor.
This commit is contained in:
Marco Elver 2014-12-23 09:31:18 -05:00
parent dd0f3943e2
commit 177682ead4
2 changed files with 27 additions and 0 deletions

View file

@ -76,6 +76,9 @@ def config_cache(options, system):
system.l2.cpu_side = system.tol2bus.master system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave system.l2.mem_side = system.membus.slave
if options.memchecker:
system.memchecker = MemChecker()
for i in xrange(options.num_cpus): for i in xrange(options.num_cpus):
if options.caches: if options.caches:
icache = icache_class(size=options.l1i_size, icache = icache_class(size=options.l1i_size,
@ -83,6 +86,21 @@ def config_cache(options, system):
dcache = dcache_class(size=options.l1d_size, dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc) assoc=options.l1d_assoc)
if options.memchecker:
dcache_mon = MemCheckerMonitor(warn_only=True)
dcache_real = dcache
# Do not pass the memchecker into the constructor of
# MemCheckerMonitor, as it would create a copy; we require
# exactly one MemChecker instance.
dcache_mon.memchecker = system.memchecker
# Connect monitor
dcache_mon.mem_side = dcache.cpu_side
# Let CPU connect to monitors
dcache = dcache_mon
# When connecting the caches, the clock is also inherited # When connecting the caches, the clock is also inherited
# from the CPU in question # from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86': if buildEnv['TARGET_ISA'] == 'x86':
@ -91,6 +109,13 @@ def config_cache(options, system):
PageTableWalkerCache()) PageTableWalkerCache())
else: else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache) system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
if options.memchecker:
# The mem_side ports of the caches haven't been connected yet.
# Make sure connectAllPorts connects the right objects.
system.cpu[i].dcache = dcache_real
system.cpu[i].dcache_mon = dcache_mon
system.cpu[i].createInterruptController() system.cpu[i].createInterruptController()
if options.l2cache: if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus) system.cpu[i].connectAllPorts(system.tol2bus, system.membus)

View file

@ -97,6 +97,8 @@ def addCommonOptions(parser):
parser.add_option("-l", "--lpae", action="store_true") parser.add_option("-l", "--lpae", action="store_true")
parser.add_option("-V", "--virtualisation", action="store_true") parser.add_option("-V", "--virtualisation", action="store_true")
parser.add_option("--memchecker", action="store_true")
# Cache Options # Cache Options
parser.add_option("--caches", action="store_true") parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true") parser.add_option("--l2cache", action="store_true")