config: Add --memchecker option
This patch adds the --memchecker option, to denote that a MemChecker should be instantiated for the system. The exact usage of the MemChecker depends on the system configuration. For now CacheConfig.py makes use of the option, adding MemCheckerMonitor instances between CPUs and D-Caches. Note, however, that currently this only provides limited checking on a running system; other parts of the system, such as I/O devices are not monitored, and may cause warnings to be issued by the monitor.
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@ -76,6 +76,9 @@ def config_cache(options, system):
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system.l2.cpu_side = system.tol2bus.master
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system.l2.cpu_side = system.tol2bus.master
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system.l2.mem_side = system.membus.slave
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system.l2.mem_side = system.membus.slave
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if options.memchecker:
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system.memchecker = MemChecker()
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for i in xrange(options.num_cpus):
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for i in xrange(options.num_cpus):
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if options.caches:
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if options.caches:
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icache = icache_class(size=options.l1i_size,
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icache = icache_class(size=options.l1i_size,
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@ -83,6 +86,21 @@ def config_cache(options, system):
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dcache = dcache_class(size=options.l1d_size,
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dcache = dcache_class(size=options.l1d_size,
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assoc=options.l1d_assoc)
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assoc=options.l1d_assoc)
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if options.memchecker:
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dcache_mon = MemCheckerMonitor(warn_only=True)
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dcache_real = dcache
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# Do not pass the memchecker into the constructor of
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# MemCheckerMonitor, as it would create a copy; we require
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# exactly one MemChecker instance.
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dcache_mon.memchecker = system.memchecker
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# Connect monitor
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dcache_mon.mem_side = dcache.cpu_side
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# Let CPU connect to monitors
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dcache = dcache_mon
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# When connecting the caches, the clock is also inherited
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# When connecting the caches, the clock is also inherited
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# from the CPU in question
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# from the CPU in question
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if buildEnv['TARGET_ISA'] == 'x86':
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if buildEnv['TARGET_ISA'] == 'x86':
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@ -91,6 +109,13 @@ def config_cache(options, system):
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PageTableWalkerCache())
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PageTableWalkerCache())
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else:
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else:
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
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if options.memchecker:
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# The mem_side ports of the caches haven't been connected yet.
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# Make sure connectAllPorts connects the right objects.
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system.cpu[i].dcache = dcache_real
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system.cpu[i].dcache_mon = dcache_mon
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system.cpu[i].createInterruptController()
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system.cpu[i].createInterruptController()
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if options.l2cache:
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if options.l2cache:
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system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
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system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
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@ -97,6 +97,8 @@ def addCommonOptions(parser):
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parser.add_option("-l", "--lpae", action="store_true")
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parser.add_option("-l", "--lpae", action="store_true")
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parser.add_option("-V", "--virtualisation", action="store_true")
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parser.add_option("-V", "--virtualisation", action="store_true")
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parser.add_option("--memchecker", action="store_true")
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# Cache Options
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# Cache Options
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parser.add_option("--caches", action="store_true")
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parser.add_option("--caches", action="store_true")
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parser.add_option("--l2cache", action="store_true")
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parser.add_option("--l2cache", action="store_true")
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