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CPU: Fix bug when a split transaction is issued to a faster cache

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In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
This commit is contained in:
Ali Saidi 2010-11-15 14:04:03 -06:00
parent 265e145db2
commit 16f210da37
2 changed files with 13 additions and 2 deletions
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11
src/cpu/simple/timing.cc
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@ -999,7 +999,16 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
if (next_tick == curTick) { if (next_tick == curTick) {
cpu->completeDataAccess(pkt); cpu->completeDataAccess(pkt);
} else { } else {
tickEvent.schedule(pkt, next_tick); if (!tickEvent.scheduled()) {
tickEvent.schedule(pkt, next_tick);
} else {
// In the case of a split transaction and a cache that is
// faster than a CPU we could get two responses before
// next_tick expires
if (!retryEvent.scheduled())
schedule(retryEvent, next_tick);
return false;
}
} }
return true; return true;

4
src/cpu/simple/timing.hh
View file

@ -140,7 +140,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
public: public:
CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
: Port(_name, _cpu), cpu(_cpu), lat(_lat) : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
{ } { }
bool snoopRangeSent; bool snoopRangeSent;
@ -161,12 +161,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
{ {
PacketPtr pkt; PacketPtr pkt;
TimingSimpleCPU *cpu; TimingSimpleCPU *cpu;
CpuPort *port;
TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {} TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
const char *description() const { return "Timing CPU tick"; } const char *description() const { return "Timing CPU tick"; }
void schedule(PacketPtr _pkt, Tick t); void schedule(PacketPtr _pkt, Tick t);
}; };
EventWrapper<Port, &Port::sendRetry> retryEvent;
}; };
class IcachePort : public CpuPort class IcachePort : public CpuPort