From 14deacf86e0d0abf1d0f558d76945ce31a0f6a0e Mon Sep 17 00:00:00 2001
From: Tony Gutierrez <anthony.gutierrez@amd.com>
Date: Mon, 21 Nov 2016 15:40:03 -0500
Subject: [PATCH] gpu-compute: fix segfault when constructing GPUExecContext

the GPUExecContext context currently stores a reference to its parent WF's
GPUISA object, however there are some special instructions that do not have
an associated WF. when these objects are constructed they set their WF pointer
to null, which causes the GPUExecContext to segfault when trying to
dereference
the WF pointer to get at the WF's GPUISA object. here we change the GPUISA
reference in the GPUExecContext class to a pointer so that it may be set to
null.
---
 src/gpu-compute/gpu_exec_context.cc | 8 +++++---
 src/gpu-compute/gpu_exec_context.hh | 2 +-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/gpu-compute/gpu_exec_context.cc b/src/gpu-compute/gpu_exec_context.cc
index ca694187c..c39bec392 100644
--- a/src/gpu-compute/gpu_exec_context.cc
+++ b/src/gpu-compute/gpu_exec_context.cc
@@ -37,7 +37,7 @@
 #include "gpu-compute/wavefront.hh"
 
 GPUExecContext::GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
-    : cu(_cu), wf(_wf), gpuISA(_wf->gpuISA())
+    : cu(_cu), wf(_wf), gpuISA(_wf ? &_wf->gpuISA() : nullptr)
 {
 }
 
@@ -56,11 +56,13 @@ GPUExecContext::wavefront()
 TheGpuISA::MiscReg
 GPUExecContext::readMiscReg(int opIdx) const
 {
-    return gpuISA.readMiscReg(opIdx);
+    assert(gpuISA);
+    return gpuISA->readMiscReg(opIdx);
 }
 
 void
 GPUExecContext::writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal)
 {
-    gpuISA.writeMiscReg(opIdx, operandVal);
+    assert(gpuISA);
+    gpuISA->writeMiscReg(opIdx, operandVal);
 }
diff --git a/src/gpu-compute/gpu_exec_context.hh b/src/gpu-compute/gpu_exec_context.hh
index f7c021c0d..513a06151 100644
--- a/src/gpu-compute/gpu_exec_context.hh
+++ b/src/gpu-compute/gpu_exec_context.hh
@@ -55,7 +55,7 @@ class GPUExecContext
   protected:
     ComputeUnit *cu;
     Wavefront *wf;
-    TheGpuISA::GPUISA &gpuISA;
+    TheGpuISA::GPUISA *gpuISA;
 };
 
 #endif // __GPU_EXEC_CONTEXT_HH__