Merge zizzer.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 849b63ae1300e240082da19dfeb283cdeeb80aef
This commit is contained in:
commit
14a7cda195
5 changed files with 72 additions and 5 deletions
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@ -311,12 +311,19 @@ def p_output_exec(t):
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def p_global_let(t):
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def p_global_let(t):
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'global_let : LET CODELIT SEMI'
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'global_let : LET CODELIT SEMI'
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updateExportContext()
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updateExportContext()
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exportContext["header_output"] = ''
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exportContext["decoder_output"] = ''
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exportContext["exec_output"] = ''
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exportContext["decode_block"] = ''
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try:
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try:
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exec fixPythonIndentation(t[2]) in exportContext
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exec fixPythonIndentation(t[2]) in exportContext
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except Exception, exc:
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except Exception, exc:
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error(t.lineno(1),
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error(t.lineno(1),
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'error: %s in global let block "%s".' % (exc, t[2]))
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'error: %s in global let block "%s".' % (exc, t[2]))
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t[0] = GenCode() # contributes nothing to the output C++ file
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t[0] = GenCode(header_output = exportContext["header_output"],
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decoder_output = exportContext["decoder_output"],
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exec_output = exportContext["exec_output"],
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decode_block = exportContext["decode_block"])
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# Define the mapping from operand type extensions to C++ types and bit
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# Define the mapping from operand type extensions to C++ types and bit
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# widths (stored in operandTypeMap).
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# widths (stored in operandTypeMap).
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@ -64,7 +64,7 @@
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0x6: push_ES();
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0x6: push_ES();
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0x7: pop_ES();
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0x7: pop_ES();
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default: MultiOp::add(
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default: MultiOp::add(
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{{out1 = in1 + in2}},
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{{Add op0, op0, op1}},
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OPCODE_OP_BOTTOM3,
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OPCODE_OP_BOTTOM3,
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[[Eb,Gb],[Ev,Gv],
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[[Eb,Gb],[Ev,Gv],
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[Gb,Eb],[Gv,Ev],
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[Gb,Eb],[Gv,Ev],
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@ -84,5 +84,8 @@ namespace X86ISA;
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//Include the definitions for the instruction formats
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//Include the definitions for the instruction formats
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##include "formats/formats.isa"
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##include "formats/formats.isa"
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//Include the definitions of the micro ops
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##include "microops/microops.isa"
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//Include the decoder definition
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//Include the decoder definition
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##include "decoder/decoder.isa"
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##include "decoder/decoder.isa"
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57
src/arch/x86/isa/microops/microops.isa
Normal file
57
src/arch/x86/isa/microops/microops.isa
Normal file
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@ -0,0 +1,57 @@
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// Copyright (c) 2007 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// Redistribution and use of this software in source and binary forms,
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// with or without modification, are permitted provided that the
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// following conditions are met:
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//
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// The software must be used only for Non-Commercial Use which means any
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// use which is NOT directed to receiving any direct monetary
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// compensation for, or commercial advantage from such use. Illustrative
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// examples of non-commercial use are academic research, personal study,
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// teaching, education and corporate research & development.
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// Illustrative examples of commercial use are distributing products for
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// commercial advantage and providing services using the software for
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// commercial advantage.
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//
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// If you wish to use this software or functionality therein that may be
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// covered by patents for commercial use, please contact:
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// Director of Intellectual Property Licensing
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// Office of Strategy and Technology
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// Hewlett-Packard Company
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// 1501 Page Mill Road
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// Palo Alto, California 94304
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer. Redistributions
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// in binary form must reproduce the above copyright notice, this list of
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// conditions and the following disclaimer in the documentation and/or
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// other materials provided with the distribution. Neither the name of
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// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission. No right of
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// sublicense is granted herewith. Derivatives of the software and
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// output created using the software may be prepared, but only for
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// Non-Commercial Uses. Derivatives of the software may be shared with
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// others provided: (i) the others agree to abide by the list of
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// conditions herein which includes the Non-Commercial Use restrictions;
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// and (ii) such Derivatives of the software include the above copyright
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// notice to acknowledge the contribution from this software where
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// applicable, this list of conditions and the disclaimer below.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//Micro ops
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##include "int.isa"
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@ -96,7 +96,7 @@ def operand_types {{
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}};
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}};
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def operands {{
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def operands {{
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# This is just copied from SPARC, because having no operands confuses
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'IntRegOp0': ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1),
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# the parser.
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'IntRegOp1': ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2),
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'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1)
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'IntRegOp2': ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2),
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}};
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}};
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