dev, mips: Remove the unused MaltaPChip class
The MaltaPChip class is currently unused and identical (except for the class name) to the TsunamiPChip. If someone decides to implement PCI for Malta, they should make sure to share code with the Tsunami implementation if they are similar.
This commit is contained in:
Andreas Sandberg
parent
00b2bd7437
commit
146dfd0356
6 changed files with 1 additions and 447 deletions
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@ -31,7 +31,6 @@ from m5.proxy import *
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from BadDevice import BadDevice
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from Device import BasicPioDevice
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from Pci import PciConfigAll
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from Platform import Platform
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from Uart import Uart8250
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@ -50,11 +49,6 @@ class MaltaIO(BasicPioDevice):
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malta = Param.Malta(Parent.any, "Malta")
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frequency = Param.Frequency('1024Hz', "frequency of interrupts")
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class MaltaPChip(BasicPioDevice):
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type = 'MaltaPChip'
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cxx_header = "dev/mips/malta_pchip.hh"
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malta = Param.Malta(Parent.any, "Malta")
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class Malta(Platform):
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type = 'Malta'
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cxx_header = "dev/mips/malta.hh"
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@ -39,4 +39,4 @@ if env['TARGET_ISA'] == 'mips':
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Source('malta.cc')
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Source('malta_cchip.cc')
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Source('malta_io.cc')
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Source('malta_pchip.cc')
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@ -43,7 +43,6 @@
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#include "dev/mips/malta.hh"
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#include "dev/mips/malta_cchip.hh"
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#include "dev/mips/malta_io.hh"
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#include "dev/mips/malta_pchip.hh"
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#include "dev/terminal.hh"
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#include "params/Malta.hh"
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#include "sim/system.hh"
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@ -43,7 +43,6 @@
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class IdeController;
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class MaltaCChip;
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class MaltaPChip;
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class MaltaIO;
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class System;
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@ -72,12 +71,6 @@ class Malta : public Platform
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*/
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MaltaCChip *cchip;
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/** Pointer to the Malta PChip.
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* The pchip is the interface to the PCI bus, in our case
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* it does not have to do much.
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*/
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MaltaPChip *pchip;
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int intr_sum_type[Malta::Max_CPUs];
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int ipi_pending[Malta::Max_CPUs];
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@ -1,337 +0,0 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Andrew Schultz
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*/
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/** @file
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* Malta PChip (pci)
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "debug/Malta.hh"
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#include "dev/mips/malta.hh"
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#include "dev/mips/malta_pchip.hh"
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#include "dev/mips/maltareg.h"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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MaltaPChip::MaltaPChip(const Params *p)
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: BasicPioDevice(p, 0x1000)
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{
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for (int i = 0; i < 4; i++) {
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wsba[i] = 0;
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wsm[i] = 0;
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tba[i] = 0;
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}
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// initialize pchip control register
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pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
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//Set back pointer in malta
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p->malta->pchip = this;
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}
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Tick
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MaltaPChip::read(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
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assert(pkt->getSize() == sizeof(uint64_t));
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DPRINTF(Malta, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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pkt->set(wsba[0]);
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break;
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case TSDEV_PC_WSBA1:
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pkt->set(wsba[1]);
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break;
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case TSDEV_PC_WSBA2:
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pkt->set(wsba[2]);
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break;
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case TSDEV_PC_WSBA3:
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pkt->set(wsba[3]);
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break;
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case TSDEV_PC_WSM0:
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pkt->set(wsm[0]);
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break;
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case TSDEV_PC_WSM1:
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pkt->set(wsm[1]);
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break;
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case TSDEV_PC_WSM2:
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pkt->set(wsm[2]);
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break;
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case TSDEV_PC_WSM3:
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pkt->set(wsm[3]);
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break;
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case TSDEV_PC_TBA0:
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pkt->set(tba[0]);
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break;
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case TSDEV_PC_TBA1:
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pkt->set(tba[1]);
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break;
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case TSDEV_PC_TBA2:
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pkt->set(tba[2]);
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break;
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case TSDEV_PC_TBA3:
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pkt->set(tba[3]);
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break;
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case TSDEV_PC_PCTL:
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pkt->set(pctl);
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break;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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pkt->set((uint64_t)0x00);
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break;
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case TSDEV_PC_PERRMASK:
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pkt->set((uint64_t)0x00);
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break;
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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pkt->set((uint64_t)0x00); // shouldn't be readable, but linux
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break;
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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MaltaPChip::write(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
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assert(pkt->getSize() == sizeof(uint64_t));
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DPRINTF(Malta, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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wsba[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA1:
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wsba[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA2:
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wsba[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA3:
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wsba[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM0:
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wsm[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM1:
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wsm[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM2:
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wsm[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM3:
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wsm[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA0:
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tba[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA1:
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tba[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA2:
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tba[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA3:
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tba[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_PCTL:
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pctl = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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break;
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case TSDEV_PC_PERRMASK:
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panic("PC_PERRMASK not implemented\n");
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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break; // value ignored, supposted to invalidate SG TLB
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip write reached reading 0x%x\n", daddr);
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} // uint64_t
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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#define DMA_ADDR_MASK ULL(0x3ffffffff)
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Addr
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MaltaPChip::translatePciToDma(Addr busAddr)
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{
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// compare the address to the window base registers
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uint64_t tbaMask = 0;
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uint64_t baMask = 0;
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uint64_t windowMask = 0;
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uint64_t windowBase = 0;
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uint64_t pteEntry = 0;
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Addr pteAddr;
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Addr dmaAddr;
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#if 0
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DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
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for (int i = 0; i < 4; i++) {
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DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
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i, wsba[i], wsm[i]);
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (ULL(0xfff) << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
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i, windowBase, windowMask, (busAddr & windowMask),
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(windowBase & windowMask));
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}
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}
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#endif
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for (int i = 0; i < 4; i++) {
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (ULL(0xfff) << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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if (wsba[i] & 0x1) { // see if enabled
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if (wsba[i] & 0x2) { // see if SG bit is set
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/** @todo
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This currently is faked by just doing a direct
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read from memory, however, to be realistic, this
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needs to actually do a bus transaction. The process
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is explained in the malta documentation on page
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10-12 and basically munges the address to look up a
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PTE from a table in memory and then uses that mapping
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to create an address for the SG page
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*/
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tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
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baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
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pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
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sys->physProxy.readBlob(pteAddr, (uint8_t*)&pteEntry,
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sizeof(uint64_t));
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dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
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} else {
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baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
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tbaMask = ~baMask;
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dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
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}
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return (dmaAddr & DMA_ADDR_MASK);
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}
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}
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}
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// if no match was found, then return the original address
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return busAddr;
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}
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Addr
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MaltaPChip::calcConfigAddr(int bus, int dev, int func)
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{
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assert(func < 8);
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assert(dev < 32);
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assert(bus == 0);
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return MaltaPciBus0Config | (func << 8) | (dev << 11);
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}
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void
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MaltaPChip::serialize(CheckpointOut &cp) const
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{
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SERIALIZE_SCALAR(pctl);
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SERIALIZE_ARRAY(wsba, 4);
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SERIALIZE_ARRAY(wsm, 4);
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SERIALIZE_ARRAY(tba, 4);
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}
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void
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MaltaPChip::unserialize(CheckpointIn &cp)
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{
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UNSERIALIZE_SCALAR(pctl);
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UNSERIALIZE_ARRAY(wsba, 4);
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UNSERIALIZE_ARRAY(wsm, 4);
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UNSERIALIZE_ARRAY(tba, 4);
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}
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MaltaPChip *
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MaltaPChipParams::create()
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{
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return new MaltaPChip(this);
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}
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@ -1,95 +0,0 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
|
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* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
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* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/** @file
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* Malta PCI interface CSRs
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*/
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#ifndef __MALTA_PCHIP_HH__
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#define __MALTA_PCHIP_HH__
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#include "dev/mips/malta.hh"
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#include "dev/io_device.hh"
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#include "params/MaltaPChip.hh"
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/**
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* A very simple implementation of the Malta PCI interface chips.
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*/
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class MaltaPChip : public BasicPioDevice
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{
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protected:
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static const Addr MaltaPciBus0Config = ULL(0x801fe000000);
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/** Pchip control register */
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uint64_t pctl;
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/** Window Base addresses */
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uint64_t wsba[4];
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/** Window masks */
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uint64_t wsm[4];
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/** Translated Base Addresses */
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uint64_t tba[4];
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public:
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typedef MaltaPChipParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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public:
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/**
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* Register the PChip with the mmu and init all wsba, wsm, and tba to 0
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* @param p pointer to the parameters struct
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*/
|
||||
MaltaPChip(const Params *p);
|
||||
|
||||
/**
|
||||
* Translate a PCI bus address to a memory address for DMA.
|
||||
* @todo Andrew says this needs to be fixed. What's wrong with it?
|
||||
* @param busAddr PCI address to translate.
|
||||
* @return memory system address
|
||||
*/
|
||||
Addr translatePciToDma(Addr busAddr);
|
||||
|
||||
Addr calcConfigAddr(int bus, int dev, int func);
|
||||
|
||||
virtual Tick read(PacketPtr pkt);
|
||||
virtual Tick write(PacketPtr pkt);
|
||||
|
||||
void serialize(CheckpointOut &cp) const override;
|
||||
void unserialize(CheckpointIn &cp) override;
|
||||
};
|
||||
|
||||
#endif // __TSUNAMI_PCHIP_HH__
|
||||
Loading…
Reference in a new issue