make the cache access latency a parameter that is based on bus

ticks for the most commonly accessed devices.

dev/baddev.cc:
    Get rid of the constant cache access latency.
    For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
    make the cache access latency a parameter that is based on bus
    ticks.
dev/io_device.cc:
dev/io_device.hh:
    add an io latency variable
dev/ns_gige.hh:
    this moved to io_device.hh

--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789

dev/baddev.cc

@@ -78,7 +78,7 @@ BadDevice::write(MemReqPtr &req, const uint8_t *data)
 Tick
 BadDevice::cacheAccess(MemReqPtr &req)
 {
-    return curTick + 1000;
+    return curTick;
 }
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
@@ -103,7 +103,8 @@ END_INIT_SIM_OBJECT_PARAMS(BadDevice)
 
 CREATE_SIM_OBJECT(BadDevice)
 {
-    return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus, devicename);
+    return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus,
+                         devicename);
 }
 
 REGISTER_SIM_OBJECT("BadDevice", BadDevice)

dev/ide_ctrl.cc

@@ -60,7 +60,7 @@ IdeController::IdeController(const string &name, IntrControl *ic,
                              MemoryController *mmu, PciConfigAll *cf,
                              PciConfigData *cd, Tsunami *t, uint32_t bus_num,
                              uint32_t dev_num, uint32_t func_num,
-                             Bus *host_bus, HierParams *hier)
+                             Bus *host_bus, Tick pio_latency, HierParams *hier)
     : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
 {
     // put back pointer into Tsunami
@@ -105,6 +105,7 @@ IdeController::IdeController(const string &name, IntrControl *ic,
 
         dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
                                              host_bus, 1);
+        pioLatency = pio_latency * host_bus->clockRatio;
     }
 
     // setup the disks attached to controller
@@ -261,7 +262,7 @@ Tick
 IdeController::cacheAccess(MemReqPtr &req)
 {
     // @todo Add more accurate timing to cache access
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 ////
@@ -700,6 +701,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
     Param<uint32_t> pci_dev;
     Param<uint32_t> pci_func;
     SimObjectParam<Bus *> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
@@ -716,6 +718,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
     INIT_PARAM(pci_dev, "PCI device number"),
     INIT_PARAM(pci_func, "PCI function code"),
     INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(IdeController)
@@ -724,7 +727,7 @@ CREATE_SIM_OBJECT(IdeController)
 {
     return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
                              configspace, configdata, tsunami, pci_bus,
-                             pci_dev, pci_func, io_bus, hier);
+                             pci_dev, pci_func, io_bus, pio_latency, hier);
 }
 
 REGISTER_SIM_OBJECT("IdeController", IdeController)

dev/ide_ctrl.hh

@@ -167,7 +167,7 @@ class IdeController : public PciDev
                   MemoryController *mmu, PciConfigAll *cf,
                   PciConfigData *cd, Tsunami *t,
                   uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
-                  Bus *host_bus, HierParams *hier);
+                  Bus *host_bus, Tick pio_latency, HierParams *hier);
 
     /**
      * Deletes the connected devices.

dev/io_device.cc

@@ -32,7 +32,7 @@
 #include "sim/builder.hh"
 
 PioDevice::PioDevice(const std::string &name)
-    : FunctionalMemory(name), pioInterface(NULL)
+    : FunctionalMemory(name), pioInterface(NULL), pioLatency(0)
 {}
 
 PioDevice::~PioDevice()

dev/io_device.hh

@@ -40,6 +40,7 @@ class PioDevice : public FunctionalMemory
 {
   protected:
     BaseInterface *pioInterface;
+    Tick pioLatency;
 
   public:
     PioDevice(const std::string &name);

dev/ns_gige.cc

@@ -120,7 +120,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
       acceptMulticast(false), acceptUnicast(false),
       acceptPerfect(false), acceptArp(false),
       physmem(pmem), intctrl(i), intrTick(0), cpuPendingIntr(false),
-      intrEvent(0), interface(0), pioLatency(pio_latency)
+      intrEvent(0), interface(0)
 {
     tsunami->ethernet = this;
 
@@ -128,6 +128,8 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
         pioInterface = newPioInterface(name, hier, header_bus, this,
                                        &NSGigE::cacheAccess);
 
+        pioLatency = pio_latency * header_bus->clockRatio;
+
         if (payload_bus)
             dmaInterface = new DMAInterface<Bus>(name + ".dma",
                                                  header_bus, payload_bus, 1);
@@ -138,9 +140,10 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
         pioInterface = newPioInterface(name, hier, payload_bus, this,
                                        &NSGigE::cacheAccess);
 
+        pioLatency = pio_latency * payload_bus->clockRatio;
+
         dmaInterface = new DMAInterface<Bus>(name + ".dma", payload_bus,
                                          payload_bus, 1);
-
     }
 
 
@@ -2659,7 +2662,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
     INIT_PARAM_DFLT(header_bus, "The IO Bus to attach to for headers", NULL),
     INIT_PARAM_DFLT(payload_bus, "The IO Bus to attach to for payload", NULL),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(dma_desc_free, "DMA of Descriptors is free", false),
     INIT_PARAM_DFLT(dma_data_free, "DMA of Data is free", false),
     INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0),

dev/ns_gige.hh

@@ -383,9 +383,6 @@ class NSGigE : public PciDev
     Stats::Formula txPacketRate;
     Stats::Formula rxPacketRate;
 
-  private:
-    Tick pioLatency;
-
   public:
     Tick cacheAccess(MemReqPtr &req);
 };

dev/pciconfigall.cc

@@ -47,7 +47,7 @@
 using namespace std;
 
 PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
-                           HierParams *hier, Bus *bus)
+                           HierParams *hier, Bus *bus, Tick pio_latency)
     : PioDevice(name), addr(a)
 {
     mmu->add_child(this, Range<Addr>(addr, addr + size));
@@ -56,6 +56,7 @@ PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
         pioInterface = newPioInterface(name, hier, bus, this,
                                       &PciConfigAll::cacheAccess);
         pioInterface->addAddrRange(addr, addr + size - 1);
+        pioLatency = pio_latency * bus->clockRatio;
     }
 
     // Make all the pointers to devices null
@@ -175,7 +176,7 @@ PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 Tick
 PciConfigAll::cacheAccess(MemReqPtr &req)
 {
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
@@ -186,6 +187,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
     Param<Addr> addr;
     Param<Addr> mask;
     SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
@@ -196,13 +198,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM(mask, "Address Mask"),
     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 
 CREATE_SIM_OBJECT(PciConfigAll)
 {
-    return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus);
+    return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
+                            pio_latency);
 }
 
 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)

dev/pciconfigall.hh

@@ -73,7 +73,7 @@ class PciConfigAll : public PioDevice
      * @param bus The bus that this device is attached to
      */
     PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
-                 HierParams *hier, Bus *bus);
+                 HierParams *hier, Bus *bus, Tick pio_latency);
 
 
     /**

dev/tsunami_cchip.cc

@@ -49,7 +49,8 @@
 using namespace std;
 
 TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
-                           MemoryController *mmu, HierParams *hier, Bus* bus)
+                           MemoryController *mmu, HierParams *hier, Bus* bus,
+                           Tick pio_latency)
     : PioDevice(name), addr(a), tsunami(t)
 {
     mmu->add_child(this, Range<Addr>(addr, addr + size));
@@ -66,6 +67,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
         pioInterface = newPioInterface(name, hier, bus, this,
                                       &TsunamiCChip::cacheAccess);
         pioInterface->addAddrRange(addr, addr + size - 1);
+        pioLatency = pio_latency * bus->clockRatio;
     }
 
     drir = 0;
@@ -383,7 +385,7 @@ TsunamiCChip::clearDRIR(uint32_t interrupt)
 Tick
 TsunamiCChip::cacheAccess(MemReqPtr &req)
 {
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 
@@ -417,6 +419,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
@@ -427,13 +430,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 
 CREATE_SIM_OBJECT(TsunamiCChip)
 {
-    return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus);
+    return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier,
+                            io_bus, pio_latency);
 }
 
 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)

dev/tsunami_cchip.hh

@@ -100,7 +100,8 @@ class TsunamiCChip : public PioDevice
      * @param bus The bus that this device is attached to
      */
     TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
-                 MemoryController *mmu, HierParams *hier, Bus *bus);
+                 MemoryController *mmu, HierParams *hier, Bus *bus,
+                 Tick pio_latency);
 
     /**
       * Process a read to the CChip.

dev/tsunami_io.cc

@@ -160,7 +160,8 @@ TsunamiIO::ClockEvent::unserialize(Checkpoint *cp, const std::string &section)
 }
 
 TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
-                     Addr a, MemoryController *mmu, HierParams *hier, Bus *bus)
+                     Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
+                     Tick pio_latency)
     : PioDevice(name), addr(a), tsunami(t), rtc(t)
 {
     mmu->add_child(this, Range<Addr>(addr, addr + size));
@@ -169,6 +170,7 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
         pioInterface = newPioInterface(name, hier, bus, this,
                                        &TsunamiIO::cacheAccess);
         pioInterface->addAddrRange(addr, addr + size - 1);
+        pioLatency = pio_latency * bus->clockRatio;
     }
 
     // set the back pointer from tsunami to myself
@@ -425,7 +427,7 @@ TsunamiIO::clearPIC(uint8_t bitvector)
 Tick
 TsunamiIO::cacheAccess(MemReqPtr &req)
 {
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 void
@@ -476,6 +478,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
@@ -488,6 +491,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
@@ -495,7 +499,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
 CREATE_SIM_OBJECT(TsunamiIO)
 {
     return new TsunamiIO(getInstanceName(), tsunami, time,  addr, mmu, hier,
-                         io_bus);
+                         io_bus, pio_latency);
 }
 
 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)

dev/tsunami_io.hh

@@ -237,7 +237,8 @@ class TsunamiIO : public PioDevice
      * @param mmu pointer to the memory controller that sends us events.
      */
     TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
-              Addr a, MemoryController *mmu, HierParams *hier, Bus *bus);
+              Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
+              Tick pio_latency);
 
     /**
      * Create the tm struct from seconds since 1970

dev/tsunami_pchip.cc

@@ -50,7 +50,7 @@ using namespace std;
 
 TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
                            MemoryController *mmu, HierParams *hier,
-                           Bus *bus)
+                           Bus *bus, Tick pio_latency)
     : PioDevice(name), addr(a), tsunami(t)
 {
     mmu->add_child(this, Range<Addr>(addr, addr + size));
@@ -65,6 +65,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
         pioInterface = newPioInterface(name, hier, bus, this,
                                       &TsunamiPChip::cacheAccess);
         pioInterface->addAddrRange(addr, addr + size - 1);
+        pioLatency = pio_latency * bus->clockRatio;
     }
 
 
@@ -351,7 +352,7 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
 Tick
 TsunamiPChip::cacheAccess(MemReqPtr &req)
 {
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
@@ -360,6 +361,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
@@ -370,13 +372,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
 
 CREATE_SIM_OBJECT(TsunamiPChip)
 {
-    return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus);
+    return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier,
+                            io_bus, pio_latency);
 }
 
 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)

dev/tsunami_pchip.hh

@@ -80,7 +80,8 @@ class TsunamiPChip : public PioDevice
      * @param bus The bus that this device is attached to
      */
     TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
-                 MemoryController *mmu, HierParams *hier, Bus *bus);
+                 MemoryController *mmu, HierParams *hier, Bus *bus,
+                 Tick pio_latency);
 
     /**
      * Translate a PCI bus address to a memory address for DMA.

dev/uart.cc

@@ -88,7 +88,7 @@ Uart::IntrEvent::scheduleIntr()
 }
 
 Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
-                         Addr s, HierParams *hier, Bus *bus, Platform *p)
+           Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
     : PioDevice(name), addr(a), size(s), cons(c), txIntrEvent(this, TX_INT),
       rxIntrEvent(this, RX_INT), platform(p)
 {
@@ -99,6 +99,7 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
         pioInterface = newPioInterface(name, hier, bus, this,
                                       &Uart::cacheAccess);
         pioInterface->addAddrRange(addr, addr + size - 1);
+        pioLatency = pio_latency * bus->clockRatio;
     }
 
     readAddr = 0;
@@ -370,7 +371,7 @@ Uart::dataAvailable()
 Tick
 Uart::cacheAccess(MemReqPtr &req)
 {
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 void
@@ -432,6 +433,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart)
     Param<Addr> addr;
     Param<Addr> size;
     SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 
@@ -445,6 +447,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Uart)
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM_DFLT(size, "Device size", 0x8),
     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(Uart)
@@ -452,7 +455,7 @@ END_INIT_SIM_OBJECT_PARAMS(Uart)
 CREATE_SIM_OBJECT(Uart)
 {
     return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus,
-                    platform);
+                    pio_latency, platform);
 }
 
 REGISTER_SIM_OBJECT("Uart", Uart)

dev/uart.hh

@@ -76,7 +76,8 @@ class Uart : public PioDevice
 
   public:
     Uart(const string &name, SimConsole *c, MemoryController *mmu,
-            Addr a, Addr s, HierParams *hier, Bus *bus, Platform *p);
+         Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
+         Platform *p);
 
     Fault read(MemReqPtr &req, uint8_t *data);
     Fault write(MemReqPtr &req, const uint8_t *data);