shuffle files around for new directory structure

--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032

SConscript

@@ -45,7 +45,7 @@ Import('env')
 # Base sources used by all configurations.
 base_sources = Split('''
 	arch/alpha/decoder.cc
-        arch/alpha/alpha_full_cpu_exec.cc
+        arch/alpha/alpha_o3_exec.cc
 	arch/alpha/fast_cpu_exec.cc
 	arch/alpha/simple_cpu_exec.cc
 	arch/alpha/full_cpu_exec.cc
@@ -89,78 +89,80 @@ base_sources = Split('''
 	base/stats/visit.cc
 	base/stats/text.cc
 
-	cpu/base_cpu.cc
+	cpu/base.cc
         cpu/base_dyn_inst.cc
 	cpu/exec_context.cc
 	cpu/exetrace.cc
 	cpu/pc_event.cc
 	cpu/static_inst.cc
-        cpu/beta_cpu/2bit_local_pred.cc
+        cpu/o3/2bit_local_pred.cc
-        cpu/beta_cpu/alpha_dyn_inst.cc
+        cpu/o3/alpha_dyn_inst.cc
-        cpu/beta_cpu/alpha_full_cpu.cc
+        cpu/o3/alpha_cpu.cc
-        cpu/beta_cpu/alpha_full_cpu_builder.cc
+        cpu/o3/alpha_cpu_builder.cc
-        cpu/beta_cpu/bpred_unit.cc
+        cpu/o3/bpred_unit.cc
-        cpu/beta_cpu/btb.cc
+        cpu/o3/btb.cc
-        cpu/beta_cpu/commit.cc
+        cpu/o3/commit.cc
-        cpu/beta_cpu/decode.cc
+        cpu/o3/decode.cc
-        cpu/beta_cpu/fetch.cc
+        cpu/o3/fetch.cc
-        cpu/beta_cpu/free_list.cc
+        cpu/o3/free_list.cc
-        cpu/beta_cpu/full_cpu.cc
+        cpu/o3/cpu.cc
-        cpu/beta_cpu/iew.cc
+        cpu/o3/iew.cc
-        cpu/beta_cpu/inst_queue.cc
+        cpu/o3/inst_queue.cc
-        cpu/beta_cpu/ldstq.cc
+        cpu/o3/ldstq.cc
-        cpu/beta_cpu/mem_dep_unit.cc
+        cpu/o3/mem_dep_unit.cc
-        cpu/beta_cpu/ras.cc
+        cpu/o3/ras.cc
-        cpu/beta_cpu/rename.cc
+        cpu/o3/rename.cc
-        cpu/beta_cpu/rename_map.cc
+        cpu/o3/rename_map.cc
-        cpu/beta_cpu/rob.cc
+        cpu/o3/rob.cc
-        cpu/beta_cpu/sat_counter.cc
+        cpu/o3/sat_counter.cc
-        cpu/beta_cpu/store_set.cc
+        cpu/o3/store_set.cc
-        cpu/beta_cpu/tournament_pred.cc
+        cpu/o3/tournament_pred.cc
-	cpu/fast_cpu/fast_cpu.cc
+	cpu/fast/cpu.cc
-	cpu/full_cpu/bpred.cc
+        cpu/sampler/sampler.cc
-	cpu/full_cpu/commit.cc
+        cpu/simple/cpu.cc
-	cpu/full_cpu/create_vector.cc
-	cpu/full_cpu/cv_spec_state.cc
-	cpu/full_cpu/dd_queue.cc
-	cpu/full_cpu/dep_link.cc
-	cpu/full_cpu/dispatch.cc
-	cpu/full_cpu/dyn_inst.cc
-	cpu/full_cpu/execute.cc
-	cpu/full_cpu/fetch.cc
-	cpu/full_cpu/floss_reasons.cc
-	cpu/full_cpu/fu_pool.cc
-	cpu/full_cpu/full_cpu.cc
-	cpu/full_cpu/inst_fifo.cc
-	cpu/full_cpu/instpipe.cc
-	cpu/full_cpu/issue.cc
-	cpu/full_cpu/ls_queue.cc
-	cpu/full_cpu/machine_queue.cc
-        cpu/full_cpu/pc_sample_profile.cc
-        cpu/full_cpu/pipetrace.cc
-        cpu/full_cpu/readyq.cc
-        cpu/full_cpu/reg_info.cc
-        cpu/full_cpu/rob_station.cc
-        cpu/full_cpu/spec_memory.cc
-        cpu/full_cpu/spec_state.cc
-        cpu/full_cpu/storebuffer.cc
-        cpu/full_cpu/writeback.cc
-        cpu/full_cpu/iq/iq_station.cc
-        cpu/full_cpu/iq/iqueue.cc
-        cpu/full_cpu/iq/segmented/chain_info.cc
-        cpu/full_cpu/iq/segmented/chain_wire.cc
-        cpu/full_cpu/iq/segmented/iq_seg.cc
-        cpu/full_cpu/iq/segmented/iq_segmented.cc
-        cpu/full_cpu/iq/segmented/seg_chain.cc
-        cpu/full_cpu/iq/seznec/iq_seznec.cc
-        cpu/full_cpu/iq/standard/iq_standard.cc
-        cpu/sampling_cpu/sampling_cpu.cc
-        cpu/simple_cpu/simple_cpu.cc
         cpu/trace/reader/mem_trace_reader.cc
         cpu/trace/reader/ibm_reader.cc
         cpu/trace/reader/itx_reader.cc
         cpu/trace/reader/m5_reader.cc
 
+	encumbered/cpu/full/bpred.cc
+	encumbered/cpu/full/commit.cc
+	encumbered/cpu/full/cpu.cc
+	encumbered/cpu/full/create_vector.cc
+	encumbered/cpu/full/cv_spec_state.cc
+	encumbered/cpu/full/dd_queue.cc
+	encumbered/cpu/full/dep_link.cc
+	encumbered/cpu/full/dispatch.cc
+	encumbered/cpu/full/dyn_inst.cc
+	encumbered/cpu/full/execute.cc
+	encumbered/cpu/full/fetch.cc
+	encumbered/cpu/full/floss_reasons.cc
+	encumbered/cpu/full/fu_pool.cc
+	encumbered/cpu/full/inst_fifo.cc
+	encumbered/cpu/full/instpipe.cc
+	encumbered/cpu/full/issue.cc
+	encumbered/cpu/full/ls_queue.cc
+	encumbered/cpu/full/machine_queue.cc
+        encumbered/cpu/full/pc_sample_profile.cc
+        encumbered/cpu/full/pipetrace.cc
+        encumbered/cpu/full/readyq.cc
+        encumbered/cpu/full/reg_info.cc
+        encumbered/cpu/full/rob_station.cc
+        encumbered/cpu/full/spec_memory.cc
+        encumbered/cpu/full/spec_state.cc
+        encumbered/cpu/full/storebuffer.cc
+        encumbered/cpu/full/writeback.cc
+        encumbered/cpu/full/iq/iq_station.cc
+        encumbered/cpu/full/iq/iqueue.cc
+        encumbered/cpu/full/iq/segmented/chain_info.cc
+        encumbered/cpu/full/iq/segmented/chain_wire.cc
+        encumbered/cpu/full/iq/segmented/iq_seg.cc
+        encumbered/cpu/full/iq/segmented/iq_segmented.cc
+        encumbered/cpu/full/iq/segmented/seg_chain.cc
+        encumbered/cpu/full/iq/seznec/iq_seznec.cc
+        encumbered/cpu/full/iq/standard/iq_standard.cc
+	encumbered/mem/functional/main.cc
+
 	mem/base_hier.cc
 	mem/base_mem.cc
 	mem/hier_params.cc
@@ -202,11 +204,10 @@ base_sources = Split('''
 	mem/cache/tags/split_lru.cc
 	mem/cache/tags/repl/gen.cc
 	mem/cache/tags/repl/repl.cc
-	mem/functional_mem/functional_memory.cc
+	mem/functional/functional.cc
-	mem/functional_mem/main_memory.cc
+	mem/timing/base_memory.cc
-	mem/timing_mem/base_memory.cc
+	mem/timing/memory_builder.cc
-	mem/timing_mem/memory_builder.cc
+	mem/timing/simple_mem_bank.cc
-	mem/timing_mem/simple_mem_bank.cc
         mem/trace/itx_writer.cc
 	mem/trace/mem_trace_writer.cc
 	mem/trace/m5_writer.cc
@@ -257,7 +258,6 @@ full_system_sources = Split('''
 	dev/baddev.cc
         dev/simconsole.cc
 	dev/disk_image.cc
-	dev/dma.cc
 	dev/etherbus.cc
 	dev/etherdump.cc
 	dev/etherint.cc
@@ -268,25 +268,12 @@ full_system_sources = Split('''
 	dev/ide_disk.cc
 	dev/io_device.cc
 	dev/ns_gige.cc
-	dev/etherdev.cc
 	dev/pciconfigall.cc
 	dev/pcidev.cc
 	dev/pktfifo.cc
-	dev/scsi.cc
+        dev/platform.cc
-	dev/scsi_ctrl.cc
-	dev/scsi_disk.cc
-	dev/scsi_none.cc
 	dev/sinic.cc
 	dev/simple_disk.cc
-	dev/tlaser_clock.cc
-	dev/tlaser_ipi.cc
-	dev/tlaser_mbox.cc
-	dev/tlaser_mc146818.cc
-	dev/tlaser_node.cc
-	dev/tlaser_pcia.cc
-	dev/tlaser_pcidev.cc
-	dev/tlaser_serial.cc
-	dev/turbolaser.cc
 	dev/tsunami.cc
 	dev/tsunami_cchip.cc
 	dev/tsunami_fake.cc
@@ -294,6 +281,22 @@ full_system_sources = Split('''
 	dev/tsunami_pchip.cc
 	dev/uart.cc
 
+	encumbered/dev/dma.cc
+	encumbered/dev/etherdev.cc
+	encumbered/dev/scsi.cc
+	encumbered/dev/scsi_ctrl.cc
+	encumbered/dev/scsi_disk.cc
+	encumbered/dev/scsi_none.cc
+	encumbered/dev/tlaser_clock.cc
+	encumbered/dev/tlaser_ipi.cc
+	encumbered/dev/tlaser_mbox.cc
+	encumbered/dev/tlaser_mc146818.cc
+	encumbered/dev/tlaser_node.cc
+	encumbered/dev/tlaser_pcia.cc
+	encumbered/dev/tlaser_pcidev.cc
+	encumbered/dev/tlaser_serial.cc
+	encumbered/dev/turbolaser.cc
+
 	kern/kernel_binning.cc
 	kern/kernel_stats.cc
 	kern/system_events.cc
@@ -307,9 +310,8 @@ full_system_sources = Split('''
 	kern/tru64/tru64_syscalls.cc
 	kern/tru64/tru64_system.cc
 
-	mem/functional_mem/memory_control.cc
+	mem/functional/memory_control.cc
-	mem/functional_mem/physical_memory.cc
+	mem/functional/physical.cc
-        dev/platform.cc
 
 	sim/system.cc
         ''')
@@ -391,7 +393,7 @@ env.Command(Split('base/traceflags.hh base/traceflags.cc'),
 # several files are generated from arch/$TARGET_ISA/isa_desc.
 env.Command(Split('''arch/alpha/decoder.cc
 		     arch/alpha/decoder.hh
-                     arch/alpha/alpha_full_cpu_exec.cc
+                     arch/alpha/alpha_o3_exec.cc
 		     arch/alpha/fast_cpu_exec.cc
                      arch/alpha/simple_cpu_exec.cc
                      arch/alpha/full_cpu_exec.cc'''),

arch/alpha/alpha_linux_process.cc

@@ -34,9 +34,9 @@
 #include <sys/types.h>
 #include <unistd.h>
 
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "sim/fake_syscall.hh"
 #include "sim/host.hh"
 #include "sim/process.hh"

arch/alpha/alpha_tru64_process.cc

@@ -44,9 +44,9 @@
 #include "arch/alpha/alpha_common_syscall_emul.hh"
 #include "arch/alpha/alpha_tru64_process.hh"
 #include "base/trace.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "sim/fake_syscall.hh"
 #include "sim/host.hh"
 #include "sim/process.hh"

arch/alpha/arguments.cc

@@ -29,7 +29,7 @@
 #include "arch/alpha/arguments.hh"
 #include "arch/alpha/vtophys.hh"
 #include "cpu/exec_context.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 
 AlphaArguments::Data::~Data()
 {

arch/alpha/ev5.cc

@@ -6,9 +6,9 @@
 #include "base/kgdb.h"
 #include "base/remote_gdb.hh"
 #include "base/stats/events.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/fast_cpu/fast_cpu.hh"
+#include "cpu/fast/cpu.hh"
 #include "kern/kernel_stats.hh"
 #include "sim/debug.hh"
 #include "sim/sim_events.hh"

arch/alpha/isa_desc

@@ -41,7 +41,7 @@ output exec {{
 #ifdef FULL_SYSTEM
 #include "arch/alpha/pseudo_inst.hh"
 #endif
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
 }};

arch/alpha/pseudo_inst.cc

@@ -35,8 +35,8 @@
 
 #include "arch/alpha/pseudo_inst.hh"
 #include "arch/alpha/vtophys.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "cpu/exec_context.hh"
 #include "kern/kernel_stats.hh"
 #include "sim/param.hh"

arch/alpha/vtophys.cc

@@ -31,7 +31,7 @@
 #include "arch/alpha/vtophys.hh"
 #include "base/trace.hh"
 #include "cpu/exec_context.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 
 using namespace std;
 

arch/isa_parser.py

@@ -628,16 +628,16 @@ class CpuModel:
 # CPU-model-specific information in this file.  Note that the ISA
 # description itself should have *no* CPU-model-specific content.
 CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
-         '#include "cpu/simple_cpu/simple_cpu.hh"',
+         '#include "cpu/simple/cpu.hh"',
          { 'CPU_exec_context': 'SimpleCPU' })
 CpuModel('FastCPU', 'fast_cpu_exec.cc',
-         '#include "cpu/fast_cpu/fast_cpu.hh"',
+         '#include "cpu/fast/cpu.hh"',
          { 'CPU_exec_context': 'FastCPU' })
 CpuModel('FullCPU', 'full_cpu_exec.cc',
-         '#include "cpu/full_cpu/dyn_inst.hh"',
+         '#include "encumbered/cpu/full/dyn_inst.hh"',
          { 'CPU_exec_context': 'DynInst' })
-CpuModel('AlphaFullCPU', 'alpha_full_cpu_exec.cc',
+CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
-         '#include "cpu/beta_cpu/alpha_dyn_inst.hh"',
+         '#include "cpu/o3/alpha_dyn_inst.hh"',
          { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
 
 # Expand template with CPU-specific references into a dictionary with

base/loader/aout_object.cc

@@ -30,7 +30,7 @@
 
 #include "base/loader/aout_object.hh"
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "base/loader/symtab.hh"
 
 #include "base/trace.hh"	// for DPRINTF

base/loader/ecoff_object.cc

@@ -30,7 +30,7 @@
 
 #include "base/loader/ecoff_object.hh"
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "base/loader/symtab.hh"
 
 #include "base/trace.hh"	// for DPRINTF

base/loader/elf_object.cc

@@ -43,7 +43,7 @@
 
 #include "base/loader/elf_object.hh"
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "base/loader/symtab.hh"
 
 #include "base/trace.hh"	// for DPRINTF

base/remote_gdb.cc

@@ -116,22 +116,20 @@
 
 #include <sys/signal.h>
 
-#include <unistd.h>
-
 #include <cstdio>
 #include <string>
+#include <unistd.h>
 
-#include "cpu/exec_context.hh"
 #include "base/intmath.hh"
 #include "base/kgdb.h"
-
-#include "mem/functional_mem/physical_memory.hh"
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"
 #include "base/trace.hh"
-#include "targetarch/vtophys.hh"
+#include "cpu/exec_context.hh"
-#include "sim/system.hh"
 #include "cpu/static_inst.hh"
+#include "mem/functional/physical.hh"
+#include "sim/system.hh"
+#include "targetarch/vtophys.hh"
 
 using namespace std;
 

cpu/base.cc

@@ -34,9 +34,9 @@
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
 #include "base/output.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "sim/param.hh"
 #include "sim/sim_events.hh"
 

cpu/base.hh

@@ -26,13 +26,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __BASE_CPU_HH__
+#ifndef __CPU_BASE_HH__
-#define __BASE_CPU_HH__
+#define __CPU_BASE_HH__
 
 #include <vector>
 
 #include "base/statistics.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 #include "targetarch/isa_traits.hh"
@@ -216,4 +216,4 @@ class BaseCPU : public SimObject
     Stats::Scalar<> numCycles;
 };
 
-#endif // __BASE_CPU_HH__
+#endif // __CPU_BASE_HH__

cpu/base_dyn_inst.cc

@@ -41,8 +41,8 @@
 #include "mem/mem_req.hh"
 
 #include "cpu/base_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
+#include "cpu/o3/alpha_cpu.hh"
 
 using namespace std;
 

cpu/base_dyn_inst.hh

@@ -34,16 +34,15 @@
 
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
-
-#include "cpu/beta_cpu/comm.hh"
 #include "cpu/exetrace.hh"
-#include "cpu/full_cpu/bpred_update.hh"
-#include "cpu/full_cpu/op_class.hh"
-#include "cpu/full_cpu/spec_memory.hh"
-#include "cpu/full_cpu/spec_state.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
 #include "cpu/static_inst.hh"
-#include "mem/functional_mem/main_memory.hh"
+#include "encumbered/cpu/full/bpred_update.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "encumbered/cpu/full/spec_memory.hh"
+#include "encumbered/cpu/full/spec_state.hh"
+#include "encumbered/mem/functional/main.hh"
 
 /**
  * @file

cpu/beta_cpu/rob.cc

@@ -1,7 +0,0 @@
-
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/rob_impl.hh"
-
-// Force instantiation of InstructionQueue.
-template class ROB<AlphaSimpleImpl>;

cpu/exec_context.cc

@@ -28,7 +28,7 @@
 
 #include <string>
 
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 
 #ifdef FULL_SYSTEM

cpu/exec_context.hh

@@ -26,12 +26,12 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __EXEC_CONTEXT_HH__
+#ifndef __CPU_EXEC_CONTEXT_HH__
-#define __EXEC_CONTEXT_HH__
+#define __CPU_EXEC_CONTEXT_HH__
 
-#include "sim/host.hh"
+#include "mem/functional/functional.hh"
 #include "mem/mem_req.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "sim/host.hh"
 #include "sim/serialize.hh"
 #include "targetarch/byte_swap.hh"
 
@@ -467,4 +467,4 @@ ExecContext::misspeculating()
     return false;
 }
 
-#endif // __EXEC_CONTEXT_HH__
+#endif // __CPU_EXEC_CONTEXT_HH__

cpu/exetrace.cc

@@ -30,13 +30,13 @@
 #include <iomanip>
 
 #include "sim/param.hh"
-#include "cpu/full_cpu/dyn_inst.hh"
+#include "encumbered/cpu/full/dyn_inst.hh"
-#include "cpu/full_cpu/spec_state.hh"
+#include "encumbered/cpu/full/spec_state.hh"
-#include "cpu/full_cpu/issue.hh"
+#include "encumbered/cpu/full/issue.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/exec_context.hh"
 #include "base/loader/symtab.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/static_inst.hh"
 
 using namespace std;

cpu/intr_control.cc

@@ -29,7 +29,7 @@
 #include <string>
 #include <vector>
 
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/intr_control.hh"
 #include "sim/builder.hh"
 #include "sim/sim_object.hh"

cpu/intr_control.hh

@@ -31,7 +31,7 @@
 
 #include <vector>
 #include "base/misc.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 #include "cpu/exec_context.hh"

cpu/memtest/memtest.cc

@@ -39,7 +39,6 @@
 #include "cpu/exec_context.hh"
 #include "cpu/memtest/memtest.hh"
 #include "mem/cache/base_cache.hh"
-#include "mem/functional_mem/main_memory.hh"
 #include "sim/builder.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"

cpu/memtest/memtest.hh

@@ -32,7 +32,7 @@
 #include <set>
 
 #include "base/statistics.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "mem/mem_interface.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_exit.hh"

cpu/o3/2bit_local_pred.cc

@@ -27,7 +27,7 @@
  */
 
 #include "base/trace.hh"
-#include "cpu/beta_cpu/2bit_local_pred.hh"
+#include "cpu/o3/2bit_local_pred.hh"
 
 DefaultBP::DefaultBP(unsigned _localPredictorSize,
                      unsigned _localCtrBits,

cpu/o3/2bit_local_pred.hh

@@ -31,7 +31,7 @@
 
 // For Addr type.
 #include "arch/alpha/isa_traits.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 class DefaultBP
 {

cpu/o3/alpha_cpu.cc

@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu_impl.hh"
+#include "cpu/o3/alpha_cpu_impl.hh"
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 // Force instantiation of AlphaFullCPU for all the implemntations that are
 // needed.  Consider merging this and alpha_dyn_inst.cc, and maybe all

cpu/o3/alpha_cpu.hh

@@ -32,7 +32,7 @@
 #ifndef __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
 #define __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
 
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/cpu.hh"
 
 template <class Impl>
 class AlphaFullCPU : public FullBetaCPU<Impl>

cpu/o3/alpha_cpu_builder.cc

@@ -26,18 +26,16 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
-
-#include "mem/cache/base_cache.hh"
-
 #include "base/inifile.hh"
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
 #include "mem/base_mem.hh"
+#include "mem/cache/base_cache.hh"
 #include "mem/mem_interface.hh"
 #include "sim/builder.hh"
 #include "sim/debug.hh"
@@ -49,16 +47,14 @@
 
 #ifdef FULL_SYSTEM
 #include "base/remote_gdb.hh"
-#include "dev/alpha_access.h"
+#include "mem/functional/memory_control.hh"
-#include "dev/pciareg.h"
+#include "mem/functional/physical.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
 #include "targetarch/vtophys.hh"
 #else // !FULL_SYSTEM
 #include "eio/eio.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #endif // FULL_SYSTEM
 
 class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>

cpu/o3/alpha_cpu_impl.hh

@@ -8,9 +8,9 @@
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
 
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
+#include "cpu/o3/alpha_cpu.hh"
-#include "cpu/beta_cpu/alpha_params.hh"
+#include "cpu/o3/alpha_params.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 #ifdef FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"

cpu/o3/alpha_dyn_inst.cc

@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst_impl.hh"
+#include "cpu/o3/alpha_dyn_inst_impl.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
 
 // Force instantiation of AlphaDynInst for all the implementations that
 // are needed.

cpu/o3/alpha_dyn_inst.hh

@@ -30,8 +30,8 @@
 #define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
 
 #include "cpu/base_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
+#include "cpu/o3/alpha_cpu.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
 #include "cpu/inst_seq.hh"
 
 /**

cpu/o3/alpha_dyn_inst_impl.hh

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,

cpu/o3/alpha_impl.hh

@@ -31,8 +31,8 @@
 
 #include "arch/alpha/isa_traits.hh"
 
-#include "cpu/beta_cpu/alpha_params.hh"
+#include "cpu/o3/alpha_params.hh"
-#include "cpu/beta_cpu/cpu_policy.hh"
+#include "cpu/o3/cpu_policy.hh"
 
 // Forward declarations.
 template <class Impl>

cpu/o3/alpha_params.hh

@@ -29,7 +29,7 @@
 #ifndef __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
 #define __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
 
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/cpu.hh"
 
 //Forward declarations
 class System;

cpu/o3/bpred_unit.cc

@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/bpred_unit_impl.hh"
+#include "cpu/o3/bpred_unit_impl.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 template class TwobitBPredUnit<AlphaSimpleImpl>;

cpu/o3/bpred_unit.hh

@@ -34,10 +34,10 @@
 #include "base/statistics.hh"
 #include "cpu/inst_seq.hh"
 
-#include "cpu/beta_cpu/2bit_local_pred.hh"
+#include "cpu/o3/2bit_local_pred.hh"
-#include "cpu/beta_cpu/tournament_pred.hh"
+#include "cpu/o3/tournament_pred.hh"
-#include "cpu/beta_cpu/btb.hh"
+#include "cpu/o3/btb.hh"
-#include "cpu/beta_cpu/ras.hh"
+#include "cpu/o3/ras.hh"
 
 #include <list>
 

cpu/o3/bpred_unit_impl.hh

@@ -28,7 +28,7 @@
 
 #include "base/trace.hh"
 #include "base/traceflags.hh"
-#include "cpu/beta_cpu/bpred_unit.hh"
+#include "cpu/o3/bpred_unit.hh"
 
 template<class Impl>
 TwobitBPredUnit<Impl>::TwobitBPredUnit(Params &params)

cpu/o3/btb.cc

@@ -28,7 +28,7 @@
 
 #include "base/intmath.hh"
 #include "base/trace.hh"
-#include "cpu/beta_cpu/btb.hh"
+#include "cpu/o3/btb.hh"
 
 DefaultBTB::DefaultBTB(unsigned _numEntries,
                        unsigned _tagBits,

cpu/o3/commit.cc

@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/commit_impl.hh"
+#include "cpu/o3/commit_impl.hh"
 
 template class SimpleCommit<AlphaSimpleImpl>;

cpu/o3/commit_impl.hh

@@ -27,7 +27,7 @@
  */
 
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/commit.hh"
+#include "cpu/o3/commit.hh"
 #include "cpu/exetrace.hh"
 
 template <class Impl>

cpu/o3/cpu.cc

@@ -33,9 +33,9 @@
 #endif
 #include "sim/root.hh"
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/cpu.hh"
 #include "cpu/exec_context.hh"
 
 using namespace std;

cpu/o3/cpu.hh

@@ -42,9 +42,9 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
-#include "cpu/beta_cpu/cpu_policy.hh"
+#include "cpu/o3/cpu_policy.hh"
 #include "cpu/exec_context.hh"
 #include "sim/process.hh"
 

cpu/o3/cpu_policy.hh

@@ -29,23 +29,23 @@
 #ifndef __CPU_BETA_CPU_CPU_POLICY_HH__
 #define __CPU_BETA_CPU_CPU_POLICY_HH__
 
-#include "cpu/beta_cpu/bpred_unit.hh"
+#include "cpu/o3/bpred_unit.hh"
-#include "cpu/beta_cpu/free_list.hh"
+#include "cpu/o3/free_list.hh"
-#include "cpu/beta_cpu/inst_queue.hh"
+#include "cpu/o3/inst_queue.hh"
-#include "cpu/beta_cpu/ldstq.hh"
+#include "cpu/o3/ldstq.hh"
-#include "cpu/beta_cpu/mem_dep_unit.hh"
+#include "cpu/o3/mem_dep_unit.hh"
-#include "cpu/beta_cpu/regfile.hh"
+#include "cpu/o3/regfile.hh"
-#include "cpu/beta_cpu/rename_map.hh"
+#include "cpu/o3/rename_map.hh"
-#include "cpu/beta_cpu/rob.hh"
+#include "cpu/o3/rob.hh"
-#include "cpu/beta_cpu/store_set.hh"
+#include "cpu/o3/store_set.hh"
 
-#include "cpu/beta_cpu/commit.hh"
+#include "cpu/o3/commit.hh"
-#include "cpu/beta_cpu/decode.hh"
+#include "cpu/o3/decode.hh"
-#include "cpu/beta_cpu/fetch.hh"
+#include "cpu/o3/fetch.hh"
-#include "cpu/beta_cpu/iew.hh"
+#include "cpu/o3/iew.hh"
-#include "cpu/beta_cpu/rename.hh"
+#include "cpu/o3/rename.hh"
 
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 template<class Impl>
 struct SimpleCPUPolicy

cpu/o3/decode.cc

@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/decode_impl.hh"
+#include "cpu/o3/decode_impl.hh"
 
 template class SimpleDecode<AlphaSimpleImpl>;

cpu/o3/decode_impl.hh

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/decode.hh"
+#include "cpu/o3/decode.hh"
 
 template<class Impl>
 SimpleDecode<Impl>::SimpleDecode(Params &params)

cpu/o3/fetch.cc

@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/fetch_impl.hh"
+#include "cpu/o3/fetch_impl.hh"
 
 template class SimpleFetch<AlphaSimpleImpl>;

cpu/o3/fetch_impl.hh

@@ -35,7 +35,7 @@
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
 #include "mem/mem_req.hh"
-#include "cpu/beta_cpu/fetch.hh"
+#include "cpu/o3/fetch.hh"
 
 #include "sim/root.hh"
 

cpu/o3/free_list.cc

@@ -28,7 +28,7 @@
 
 #include "base/trace.hh"
 
-#include "cpu/beta_cpu/free_list.hh"
+#include "cpu/o3/free_list.hh"
 
 SimpleFreeList::SimpleFreeList(unsigned _numLogicalIntRegs,
                                unsigned _numPhysicalIntRegs,

cpu/o3/free_list.hh

@@ -35,7 +35,7 @@
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 /**
  * FreeList class that simply holds the list of free integer and floating

cpu/o3/iew.cc

@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/iew_impl.hh"
+#include "cpu/o3/iew_impl.hh"
-#include "cpu/beta_cpu/inst_queue.hh"
+#include "cpu/o3/inst_queue.hh"
 
 template class SimpleIEW<AlphaSimpleImpl>;

cpu/o3/iew.hh

@@ -37,7 +37,7 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 template<class Impl>
 class SimpleIEW

cpu/o3/iew_impl.hh

@@ -34,7 +34,7 @@
 #include <queue>
 
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/iew.hh"
+#include "cpu/o3/iew.hh"
 
 template<class Impl>
 SimpleIEW<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst,

cpu/o3/inst_queue.cc

@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/inst_queue_impl.hh"
+#include "cpu/o3/inst_queue_impl.hh"
 
 // Force instantiation of InstructionQueue.
 template class InstructionQueue<AlphaSimpleImpl>;

cpu/o3/inst_queue_impl.hh

@@ -38,7 +38,7 @@
 
 #include "sim/root.hh"
 
-#include "cpu/beta_cpu/inst_queue.hh"
+#include "cpu/o3/inst_queue.hh"
 
 // Either compile error or max int due to sign extension.
 // Hack to avoid compile warnings.

cpu/o3/mem_dep_unit.cc

@@ -26,10 +26,10 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/store_set.hh"
+#include "cpu/o3/store_set.hh"
-#include "cpu/beta_cpu/mem_dep_unit_impl.hh"
+#include "cpu/o3/mem_dep_unit_impl.hh"
 
 // Force instantation of memory dependency unit using store sets and
 // AlphaSimpleImpl.

cpu/o3/mem_dep_unit_impl.hh

@@ -28,7 +28,7 @@
 
 #include <map>
 
-#include "cpu/beta_cpu/mem_dep_unit.hh"
+#include "cpu/o3/mem_dep_unit.hh"
 
 template <class MemDepPred, class Impl>
 MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params &params)

cpu/o3/ras.cc

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/ras.hh"
+#include "cpu/o3/ras.hh"
 
 ReturnAddrStack::ReturnAddrStack(unsigned _numEntries)
     : numEntries(_numEntries), usedEntries(0),

cpu/o3/regfile.hh

@@ -33,7 +33,7 @@
 
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 #ifdef FULL_SYSTEM
 #include "arch/alpha/ev5.hh"

cpu/o3/rename.cc

@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
-#include "cpu/beta_cpu/rename_impl.hh"
+#include "cpu/o3/rename_impl.hh"
 
 template class SimpleRename<AlphaSimpleImpl>;

cpu/o3/rename_impl.hh

@@ -28,7 +28,7 @@
 
 #include <list>
 
-#include "cpu/beta_cpu/rename.hh"
+#include "cpu/o3/rename.hh"
 
 template <class Impl>
 SimpleRename<Impl>::SimpleRename(Params &params)

cpu/o3/rename_map.cc

@@ -28,7 +28,7 @@
 
 #include <vector>
 
-#include "cpu/beta_cpu/rename_map.hh"
+#include "cpu/o3/rename_map.hh"
 
 using namespace std;
 

cpu/o3/rename_map.hh

@@ -37,7 +37,7 @@
 #include <utility>
 #include <vector>
 
-#include "cpu/beta_cpu/free_list.hh"
+#include "cpu/o3/free_list.hh"
 
 class SimpleRenameMap
 {

cpu/o3/rob.cc

@@ -0,0 +1,7 @@
+
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/rob_impl.hh"
+
+// Force instantiation of InstructionQueue.
+template class ROB<AlphaSimpleImpl>;

cpu/o3/rob_impl.hh

@@ -29,7 +29,7 @@
 #ifndef __CPU_BETA_CPU_ROB_IMPL_HH__
 #define __CPU_BETA_CPU_ROB_IMPL_HH__
 
-#include "cpu/beta_cpu/rob.hh"
+#include "cpu/o3/rob.hh"
 
 template <class Impl>
 ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth)

cpu/o3/sat_counter.cc

@@ -27,7 +27,7 @@
  */
 
 #include "base/misc.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 SatCounter::SatCounter()
     : maxVal(0), counter(0)

cpu/o3/store_set.cc

@@ -27,7 +27,7 @@
  */
 
 #include "base/trace.hh"
-#include "cpu/beta_cpu/store_set.hh"
+#include "cpu/o3/store_set.hh"
 
 StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
     : SSIT_size(_SSIT_size), LFST_size(_LFST_size)

cpu/o3/tournament_pred.cc

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/tournament_pred.hh"
+#include "cpu/o3/tournament_pred.hh"
 
 TournamentBP::TournamentBP(unsigned _local_predictor_size,
                            unsigned _local_ctr_bits,

cpu/o3/tournament_pred.hh

@@ -31,7 +31,7 @@
 
 // For Addr type.
 #include "arch/alpha/isa_traits.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 class TournamentBP
 {

cpu/ozone/cpu.hh

@@ -30,9 +30,9 @@
 #define __CPU_OOO_CPU_OOO_CPU_HH__
 
 #include "base/statistics.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/full_cpu/fu_pool.hh"
+#include "encumbered/cpu/full/fu_pool.hh"
 #include "cpu/ooo_cpu/ea_list.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/static_inst.hh"

cpu/pc_event.cc

@@ -32,7 +32,7 @@
 #include <utility>
 
 #include "base/trace.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
 #include "sim/debug.hh"

cpu/simple/cpu.cc

@@ -41,14 +41,14 @@
 #include "base/misc.hh"
 #include "base/pollevent.hh"
 #include "base/range.hh"
-#include "base/trace.hh"
 #include "base/stats/events.hh"
-#include "cpu/base_cpu.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
-#include "cpu/full_cpu/smt.hh"
+#include "cpu/sampler/sampler.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/simple/cpu.hh"
-#include "cpu/simple_cpu/simple_cpu.hh"
+#include "cpu/smt.hh"
 #include "cpu/static_inst.hh"
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
@@ -61,16 +61,14 @@
 
 #ifdef FULL_SYSTEM
 #include "base/remote_gdb.hh"
-#include "dev/alpha_access.h"
+#include "mem/functional/memory_control.hh"
-#include "dev/pciareg.h"
+#include "mem/functional/physical.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
 #include "targetarch/vtophys.hh"
 #else // !FULL_SYSTEM
 #include "eio/eio.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #endif // FULL_SYSTEM
 
 using namespace std;

cpu/simple/cpu.hh

@@ -30,10 +30,10 @@
 #define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
 
 #include "base/statistics.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "cpu/static_inst.hh"
 #include "sim/eventq.hh"
 

cpu/static_inst.hh

@@ -32,11 +32,10 @@
 #include <bitset>
 #include <string>
 
-#include "sim/host.hh"
 #include "base/hashmap.hh"
 #include "base/refcnt.hh"
-
+#include "encumbered/cpu/full/op_class.hh"
-#include "cpu/full_cpu/op_class.hh"
+#include "sim/host.hh"
 #include "targetarch/isa_traits.hh"
 
 // forward declarations

dev/alpha_console.cc

@@ -37,16 +37,16 @@
 #include "base/inifile.hh"
 #include "base/str.hh"	// for to_number()
 #include "base/trace.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "dev/alpha_console.hh"
 #include "dev/simconsole.hh"
 #include "dev/simple_disk.hh"
-#include "dev/tlaser_clock.hh"
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 #include "dev/tsunami_io.hh"

dev/baddev.cc

@@ -41,7 +41,7 @@
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 

dev/ide_ctrl.cc

@@ -33,7 +33,6 @@
 
 #include "base/trace.hh"
 #include "cpu/intr_control.hh"
-#include "dev/dma.hh"
 #include "dev/ide_ctrl.hh"
 #include "dev/ide_disk.hh"
 #include "dev/pciconfigall.hh"
@@ -43,8 +42,8 @@
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "sim/sim_object.hh"
 

dev/ide_disk.cc

@@ -42,7 +42,7 @@
 #include "dev/ide_ctrl.hh"
 #include "dev/tsunami.hh"
 #include "dev/tsunami_pchip.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 #include "mem/bus/bus.hh"
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"

dev/io_device.hh

@@ -29,7 +29,7 @@
 #ifndef __DEV_IO_DEVICE_HH__
 #define __DEV_IO_DEVICE_HH__
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 
 class BaseInterface;
 class Bus;

dev/ns_gige.cc

@@ -36,7 +36,6 @@
 
 #include "base/inet.hh"
 #include "cpu/exec_context.hh"
-#include "dev/dma.hh"
 #include "dev/etherlink.hh"
 #include "dev/ns_gige.hh"
 #include "dev/pciconfigall.hh"
@@ -44,8 +43,8 @@
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"

dev/pciconfigall.cc

@@ -42,7 +42,7 @@
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 

dev/pcidev.cc

@@ -39,11 +39,10 @@
 #include "base/misc.hh"
 #include "base/str.hh"	// for to_number
 #include "base/trace.hh"
-#include "dev/pciareg.h"
 #include "dev/pcidev.hh"
 #include "dev/pciconfigall.hh"
 #include "mem/bus/bus.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/param.hh"
 #include "sim/root.hh"