Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed.
src/arch/alpha/syscallreturn.hh: src/arch/mips/syscallreturn.hh: src/sim/syscallreturn.hh: Move the SyscallReturn class into sim/syscallreturn.hh src/arch/sparc/faults.cc: src/arch/sparc/isa/operands.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/arch/sparc/process.cc: src/arch/sparc/sparc_traits.hh: Move some miscregs into the integer register file so they get renamed. --HG-- extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
This commit is contained in:
parent
f2daf210f1
commit
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11 changed files with 182 additions and 173 deletions
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@ -32,38 +32,7 @@
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#ifndef __ARCH_ALPHA_SYSCALLRETURN_HH__
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#ifndef __ARCH_ALPHA_SYSCALLRETURN_HH__
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#define __ARCH_ALPHA_SYSCALLRETURN_HH__
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#define __ARCH_ALPHA_SYSCALLRETURN_HH__
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class SyscallReturn {
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#include "sim/syscallreturn.hh"
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public:
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template <class T>
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SyscallReturn(T v, bool s)
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{
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retval = (uint64_t)v;
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success = s;
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}
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template <class T>
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SyscallReturn(T v)
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{
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success = (v >= 0);
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retval = (uint64_t)v;
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}
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~SyscallReturn() {}
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SyscallReturn& operator=(const SyscallReturn& s) {
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retval = s.retval;
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success = s.success;
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return *this;
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}
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bool successful() { return success; }
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uint64_t value() { return retval; }
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private:
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uint64_t retval;
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bool success;
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};
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namespace AlphaISA
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namespace AlphaISA
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{
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{
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@ -32,38 +32,7 @@
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#ifndef __ARCH_MIPS_SYSCALLRETURN_HH__
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#ifndef __ARCH_MIPS_SYSCALLRETURN_HH__
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#define __ARCH_MIPS_SYSCALLRETURN_HH__
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#define __ARCH_MIPS_SYSCALLRETURN_HH__
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class SyscallReturn {
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#include "sim/syscallreturn.hh"
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public:
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template <class T>
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SyscallReturn(T v, bool s)
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{
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retval = (uint32_t)v;
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success = s;
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}
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template <class T>
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SyscallReturn(T v)
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{
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success = (v >= 0);
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retval = (uint32_t)v;
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}
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~SyscallReturn() {}
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SyscallReturn& operator=(const SyscallReturn& s) {
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retval = s.retval;
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success = s.success;
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return *this;
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}
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bool successful() { return success; }
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uint64_t value() { return retval; }
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private:
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uint64_t retval;
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bool success;
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};
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namespace MipsISA
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namespace MipsISA
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{
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{
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@ -302,10 +302,12 @@ void doREDFault(ThreadContext *tc, TrapType tt)
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MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
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//MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
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MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
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MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
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MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
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MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
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MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
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MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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//MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3);
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MiscReg GL = tc->readMiscReg(MISCREG_GL);
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MiscReg GL = tc->readMiscReg(MISCREG_GL);
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MiscReg PC = tc->readPC();
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MiscReg PC = tc->readPC();
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MiscReg NPC = tc->readNextPC();
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MiscReg NPC = tc->readNextPC();
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@ -396,10 +398,12 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
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MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
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//MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
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MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
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MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
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MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
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MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
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MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
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MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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//MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
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MiscReg GL = tc->readMiscReg(MISCREG_GL);
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MiscReg GL = tc->readMiscReg(MISCREG_GL);
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MiscReg PC = tc->readPC();
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MiscReg PC = tc->readPC();
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MiscReg NPC = tc->readNextPC();
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MiscReg NPC = tc->readNextPC();
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@ -56,12 +56,23 @@ def operands {{
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# Int regs default to unsigned, but code should not count on this.
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# Int regs default to unsigned, but code should not count on this.
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# For clarity, descriptions that depend on unsigned behavior should
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# For clarity, descriptions that depend on unsigned behavior should
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# explicitly specify '.uq'.
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# explicitly specify '.uq'.
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'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
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'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
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'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
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# The Rd from the previous window
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'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
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'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
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'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
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# The Rd from the next window
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'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
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'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
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'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6),
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# The low (even) register of a two register pair
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'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
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# The high (odd) register of a two register pair
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'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
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'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
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'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
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# A microcode register. Right now, this is the only one.
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'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
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# Because double and quad precision register numbers are decoded
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# differently, they get different operands. The single precision versions
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# have an s post pended to their name.
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'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
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'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
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'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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# Each Frd_N refers to the Nth double precision register from Frd.
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# Each Frd_N refers to the Nth double precision register from Frd.
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'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
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'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
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'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
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'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
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# Registers which are used explicitly in instructions
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'R0': ('IntReg', 'udw', '0', None, 6),
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'R0': ('IntReg', 'udw', '0', None, 6),
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'R1': ('IntReg', 'udw', '1', None, 7),
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'R1': ('IntReg', 'udw', '1', None, 7),
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'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
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'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
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'R16': ('IntReg', 'udw', '16', None, 9),
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'R16': ('IntReg', 'udw', '16', None, 9),
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# Control registers
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# Control registers
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'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
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# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
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'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
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# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
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'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
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'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
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'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
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'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
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'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
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'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
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'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
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'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
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'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
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'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
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'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
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'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
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'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
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'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
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'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
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'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing']), 62),
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'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
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# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
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'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
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# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
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'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
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# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
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'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
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# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
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'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
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# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
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'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
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'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
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'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
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'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
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'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
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'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
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'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
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'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
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'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
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@ -58,8 +58,8 @@ namespace SparcISA
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// These enumerate all the registers for dependence tracking.
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// These enumerate all the registers for dependence tracking.
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enum DependenceTags {
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enum DependenceTags {
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FP_Base_DepTag = 33,
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FP_Base_DepTag = 32*3+8,
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Ctrl_Base_DepTag = 97,
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Ctrl_Base_DepTag = FP_Base_DepTag + 64,
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};
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};
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// semantically meaningful register indices
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// semantically meaningful register indices
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@ -50,12 +50,12 @@ class Checkpoint;
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string SparcISA::getMiscRegName(RegIndex index)
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string SparcISA::getMiscRegName(RegIndex index)
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{
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{
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static::string miscRegName[NumMiscRegs] =
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static::string miscRegName[NumMiscRegs] =
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{"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
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{/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
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"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
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"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
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"stick", "stick_cmpr",
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"stick", "stick_cmpr",
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"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
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"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
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"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
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"pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
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"wstate", "gl",
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"wstate",*/ "gl",
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"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
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"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
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"hstick_cmpr",
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"hstick_cmpr",
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"fsr"};
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"fsr"};
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MiscReg MiscRegFile::readReg(int miscReg)
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MiscReg MiscRegFile::readReg(int miscReg)
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{
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{
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switch (miscReg) {
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switch (miscReg) {
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case MISCREG_Y:
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// case MISCREG_Y:
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return y;
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// return y;
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case MISCREG_CCR:
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// case MISCREG_CCR:
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return ccr;
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// return ccr;
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case MISCREG_ASI:
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case MISCREG_ASI:
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return asi;
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return asi;
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case MISCREG_FPRS:
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case MISCREG_FPRS:
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return pil;
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return pil;
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case MISCREG_CWP:
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case MISCREG_CWP:
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return cwp;
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return cwp;
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case MISCREG_CANSAVE:
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// case MISCREG_CANSAVE:
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return cansave;
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// return cansave;
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case MISCREG_CANRESTORE:
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// case MISCREG_CANRESTORE:
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return canrestore;
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// return canrestore;
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case MISCREG_CLEANWIN:
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// case MISCREG_CLEANWIN:
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return cleanwin;
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// return cleanwin;
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case MISCREG_OTHERWIN:
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// case MISCREG_OTHERWIN:
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return otherwin;
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// return otherwin;
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case MISCREG_WSTATE:
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// case MISCREG_WSTATE:
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return wstate;
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// return wstate;
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case MISCREG_GL:
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case MISCREG_GL:
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return gl;
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return gl;
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@ -225,12 +225,12 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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void MiscRegFile::setReg(int miscReg, const MiscReg &val)
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void MiscRegFile::setReg(int miscReg, const MiscReg &val)
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{
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{
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switch (miscReg) {
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switch (miscReg) {
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case MISCREG_Y:
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// case MISCREG_Y:
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y = val;
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// y = val;
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break;
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// break;
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case MISCREG_CCR:
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// case MISCREG_CCR:
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ccr = val;
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// ccr = val;
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break;
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// break;
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case MISCREG_ASI:
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case MISCREG_ASI:
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asi = val;
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asi = val;
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break;
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break;
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@ -291,21 +291,21 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
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case MISCREG_CWP:
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case MISCREG_CWP:
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cwp = val;
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cwp = val;
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break;
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break;
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case MISCREG_CANSAVE:
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// case MISCREG_CANSAVE:
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cansave = val;
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// cansave = val;
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break;
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// break;
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case MISCREG_CANRESTORE:
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// case MISCREG_CANRESTORE:
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canrestore = val;
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// canrestore = val;
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break;
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// break;
|
||||||
case MISCREG_CLEANWIN:
|
// case MISCREG_CLEANWIN:
|
||||||
cleanwin = val;
|
// cleanwin = val;
|
||||||
break;
|
// break;
|
||||||
case MISCREG_OTHERWIN:
|
// case MISCREG_OTHERWIN:
|
||||||
otherwin = val;
|
// otherwin = val;
|
||||||
break;
|
// break;
|
||||||
case MISCREG_WSTATE:
|
// case MISCREG_WSTATE:
|
||||||
wstate = val;
|
// wstate = val;
|
||||||
break;
|
// break;
|
||||||
case MISCREG_GL:
|
case MISCREG_GL:
|
||||||
gl = val;
|
gl = val;
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -48,8 +48,8 @@ namespace SparcISA
|
||||||
enum MiscRegIndex
|
enum MiscRegIndex
|
||||||
{
|
{
|
||||||
/** Ancillary State Registers */
|
/** Ancillary State Registers */
|
||||||
MISCREG_Y,
|
// MISCREG_Y,
|
||||||
MISCREG_CCR,
|
// MISCREG_CCR,
|
||||||
MISCREG_ASI,
|
MISCREG_ASI,
|
||||||
MISCREG_TICK,
|
MISCREG_TICK,
|
||||||
MISCREG_FPRS,
|
MISCREG_FPRS,
|
||||||
|
@ -74,11 +74,11 @@ namespace SparcISA
|
||||||
MISCREG_TL,
|
MISCREG_TL,
|
||||||
MISCREG_PIL,
|
MISCREG_PIL,
|
||||||
MISCREG_CWP,
|
MISCREG_CWP,
|
||||||
MISCREG_CANSAVE,
|
// MISCREG_CANSAVE,
|
||||||
MISCREG_CANRESTORE,
|
// MISCREG_CANRESTORE,
|
||||||
MISCREG_CLEANWIN,
|
// MISCREG_CLEANWIN,
|
||||||
MISCREG_OTHERWIN,
|
// MISCREG_OTHERWIN,
|
||||||
MISCREG_WSTATE,
|
// MISCREG_WSTATE,
|
||||||
MISCREG_GL,
|
MISCREG_GL,
|
||||||
|
|
||||||
/** Hyper privileged registers */
|
/** Hyper privileged registers */
|
||||||
|
|
|
@ -95,17 +95,22 @@ SparcLiveProcess::startup()
|
||||||
*/
|
*/
|
||||||
|
|
||||||
//No windows contain info from other programs
|
//No windows contain info from other programs
|
||||||
threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
|
//threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
|
||||||
|
threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
|
||||||
//There are no windows to pop
|
//There are no windows to pop
|
||||||
threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
|
//threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
|
||||||
|
threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0);
|
||||||
//All windows are available to save into
|
//All windows are available to save into
|
||||||
threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
|
//threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
|
||||||
|
threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2);
|
||||||
//All windows are "clean"
|
//All windows are "clean"
|
||||||
threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
|
//threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
|
||||||
|
threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows);
|
||||||
//Start with register window 0
|
//Start with register window 0
|
||||||
threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
|
threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
|
||||||
//Always use spill and fill traps 0
|
//Always use spill and fill traps 0
|
||||||
threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
|
//threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
|
||||||
|
threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
|
||||||
//Set the trap level to 0
|
//Set the trap level to 0
|
||||||
threadContexts[0]->setMiscReg(MISCREG_TL, 0);
|
threadContexts[0]->setMiscReg(MISCREG_TL, 0);
|
||||||
//Set the ASI register to something fixed
|
//Set the ASI register to something fixed
|
||||||
|
|
|
@ -41,7 +41,8 @@ namespace SparcISA
|
||||||
|
|
||||||
// Number of register windows, can legally be 3 to 32
|
// Number of register windows, can legally be 3 to 32
|
||||||
const int NWindows = 8;
|
const int NWindows = 8;
|
||||||
const int NumMicroIntRegs = 1;
|
//const int NumMicroIntRegs = 1;
|
||||||
|
const int NumMicroIntRegs = 8;
|
||||||
|
|
||||||
// const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16;
|
// const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16;
|
||||||
// const int NumMicroIntRegs = 1;
|
// const int NumMicroIntRegs = 1;
|
||||||
|
|
|
@ -33,58 +33,30 @@
|
||||||
|
|
||||||
#include <inttypes.h>
|
#include <inttypes.h>
|
||||||
|
|
||||||
|
#include "sim/syscallreturn.hh"
|
||||||
#include "arch/sparc/regfile.hh"
|
#include "arch/sparc/regfile.hh"
|
||||||
|
#include "cpu/thread_context.hh"
|
||||||
class SyscallReturn
|
|
||||||
{
|
|
||||||
public:
|
|
||||||
template <class T>
|
|
||||||
SyscallReturn(T v, bool s)
|
|
||||||
{
|
|
||||||
retval = (uint64_t)v;
|
|
||||||
success = s;
|
|
||||||
}
|
|
||||||
|
|
||||||
template <class T>
|
|
||||||
SyscallReturn(T v)
|
|
||||||
{
|
|
||||||
success = (v >= 0);
|
|
||||||
retval = (uint64_t)v;
|
|
||||||
}
|
|
||||||
|
|
||||||
~SyscallReturn() {}
|
|
||||||
|
|
||||||
SyscallReturn& operator=(const SyscallReturn& s)
|
|
||||||
{
|
|
||||||
retval = s.retval;
|
|
||||||
success = s.success;
|
|
||||||
return *this;
|
|
||||||
}
|
|
||||||
|
|
||||||
bool successful() { return success; }
|
|
||||||
uint64_t value() { return retval; }
|
|
||||||
|
|
||||||
private:
|
|
||||||
uint64_t retval;
|
|
||||||
bool success;
|
|
||||||
};
|
|
||||||
|
|
||||||
namespace SparcISA
|
namespace SparcISA
|
||||||
{
|
{
|
||||||
static inline void setSyscallReturn(SyscallReturn return_value,
|
static inline void setSyscallReturn(SyscallReturn return_value,
|
||||||
RegFile *regs)
|
ThreadContext * tc)
|
||||||
{
|
{
|
||||||
// check for error condition. SPARC syscall convention is to
|
// check for error condition. SPARC syscall convention is to
|
||||||
// indicate success/failure in reg the carry bit of the ccr
|
// indicate success/failure in reg the carry bit of the ccr
|
||||||
// and put the return value itself in the standard return value reg ().
|
// and put the return value itself in the standard return value reg ().
|
||||||
if (return_value.successful()) {
|
if (return_value.successful()) {
|
||||||
// no error, clear XCC.C
|
// no error, clear XCC.C
|
||||||
regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEE);
|
tc->setIntReg(NumIntArchRegs + 2,
|
||||||
regs->setIntReg(ReturnValueReg, return_value.value());
|
tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
|
||||||
|
//tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) & 0xEE);
|
||||||
|
tc->setIntReg(ReturnValueReg, return_value.value());
|
||||||
} else {
|
} else {
|
||||||
// got an error, set XCC.C
|
// got an error, set XCC.C
|
||||||
regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x11);
|
tc->setIntReg(NumIntArchRegs + 2,
|
||||||
regs->setIntReg(ReturnValueReg, return_value.value());
|
tc->readIntReg(NumIntArchRegs + 2) | 0x11);
|
||||||
|
//tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) | 0x11);
|
||||||
|
tc->setIntReg(ReturnValueReg, return_value.value());
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
70
src/sim/syscallreturn.hh
Normal file
70
src/sim/syscallreturn.hh
Normal file
|
@ -0,0 +1,70 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __SIM_SYSCALLRETURN_HH__
|
||||||
|
#define __SIM_SYSCALLRETURN_HH__
|
||||||
|
|
||||||
|
#include <inttypes.h>
|
||||||
|
|
||||||
|
class SyscallReturn
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
template <class T>
|
||||||
|
SyscallReturn(T v, bool s)
|
||||||
|
{
|
||||||
|
retval = (uint64_t)v;
|
||||||
|
success = s;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class T>
|
||||||
|
SyscallReturn(T v)
|
||||||
|
{
|
||||||
|
success = (v >= 0);
|
||||||
|
retval = (uint64_t)v;
|
||||||
|
}
|
||||||
|
|
||||||
|
~SyscallReturn() {}
|
||||||
|
|
||||||
|
SyscallReturn& operator=(const SyscallReturn& s)
|
||||||
|
{
|
||||||
|
retval = s.retval;
|
||||||
|
success = s.success;
|
||||||
|
return *this;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool successful() { return success; }
|
||||||
|
uint64_t value() { return retval; }
|
||||||
|
|
||||||
|
private:
|
||||||
|
uint64_t retval;
|
||||||
|
bool success;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
Loading…
Reference in a new issue