sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ruby: mesi cmp directory: separate actions for external hits

Browse source 
This patch adds separate actions for requests that missed in the local cache
and messages were sent out to get the requested line. These separate actions
are required for differentiating between the hit and miss latencies in the
statistics collected.
This commit is contained in:
Nilay Vaish 2013-06-25 00:32:03 -05:00
parent beb6e57c6f
commit 128ab50c47
1 changed files with 31 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
src/mem/protocol/MESI_CMP_directory-L1cache.sm
View file

@ -790,19 +790,40 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
sequencer.invalidateSC(address); sequencer.invalidateSC(address);
} }
action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") { action(h_load_hit, "h",
desc="If not prefetch, notify sequencer the load completed.")
{
assert(is_valid(cache_entry)); assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
sequencer.readCallback(address, cache_entry.DataBlk); sequencer.readCallback(address, cache_entry.DataBlk);
} }
action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") { action(hx_load_hit, "hx",
desc="If not prefetch, notify sequencer the load completed.")
{
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
sequencer.readCallback(address, cache_entry.DataBlk, true);
}
action(hh_store_hit, "\h",
desc="If not prefetch, notify sequencer that store completed.")
{
assert(is_valid(cache_entry)); assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
sequencer.writeCallback(address, cache_entry.DataBlk); sequencer.writeCallback(address, cache_entry.DataBlk);
cache_entry.Dirty := true; cache_entry.Dirty := true;
} }
action(hhx_store_hit, "\hx",
desc="If not prefetch, notify sequencer that store completed.")
{
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
sequencer.writeCallback(address, cache_entry.DataBlk, true);
cache_entry.Dirty := true;
}
action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") { action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
check_allocate(L1_TBEs); check_allocate(L1_TBEs);
assert(is_valid(cache_entry)); assert(is_valid(cache_entry));
@ -1158,7 +1179,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
transition(IS, Data_all_Acks, S) { transition(IS, Data_all_Acks, S) {
u_writeDataToL1Cache; u_writeDataToL1Cache;
h_load_hit; hx_load_hit;
s_deallocateTBE; s_deallocateTBE;
o_popIncomingResponseQueue; o_popIncomingResponseQueue;
kd_wakeUpDependents; kd_wakeUpDependents;
@ -1174,7 +1195,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
transition(IS_I, Data_all_Acks, I) { transition(IS_I, Data_all_Acks, I) {
u_writeDataToL1Cache; u_writeDataToL1Cache;
h_load_hit; hx_load_hit;
s_deallocateTBE; s_deallocateTBE;
o_popIncomingResponseQueue; o_popIncomingResponseQueue;
kd_wakeUpDependents; kd_wakeUpDependents;
@ -1189,7 +1210,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
transition(IS, DataS_fromL1, S) { transition(IS, DataS_fromL1, S) {
u_writeDataToL1Cache; u_writeDataToL1Cache;
j_sendUnblock; j_sendUnblock;
h_load_hit; hx_load_hit;
s_deallocateTBE; s_deallocateTBE;
o_popIncomingResponseQueue; o_popIncomingResponseQueue;
kd_wakeUpDependents; kd_wakeUpDependents;
@ -1206,7 +1227,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
transition(IS_I, DataS_fromL1, I) { transition(IS_I, DataS_fromL1, I) {
u_writeDataToL1Cache; u_writeDataToL1Cache;
j_sendUnblock; j_sendUnblock;
h_load_hit; hx_load_hit;
s_deallocateTBE; s_deallocateTBE;
o_popIncomingResponseQueue; o_popIncomingResponseQueue;
kd_wakeUpDependents; kd_wakeUpDependents;
@ -1222,7 +1243,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
// directory is blocked when sending exclusive data // directory is blocked when sending exclusive data
transition(IS_I, Data_Exclusive, E) { transition(IS_I, Data_Exclusive, E) {
u_writeDataToL1Cache; u_writeDataToL1Cache;
h_load_hit; hx_load_hit;
jj_sendExclusiveUnblock; jj_sendExclusiveUnblock;
s_deallocateTBE; s_deallocateTBE;
o_popIncomingResponseQueue; o_popIncomingResponseQueue;
@ -1240,7 +1261,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
transition(IS, Data_Exclusive, E) { transition(IS, Data_Exclusive, E) {
u_writeDataToL1Cache; u_writeDataToL1Cache;
h_load_hit; hx_load_hit;
jj_sendExclusiveUnblock; jj_sendExclusiveUnblock;
s_deallocateTBE; s_deallocateTBE;
o_popIncomingResponseQueue; o_popIncomingResponseQueue;
@ -1281,7 +1302,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
transition(IM, Data_all_Acks, M) { transition(IM, Data_all_Acks, M) {
u_writeDataToL1Cache; u_writeDataToL1Cache;
hh_store_hit; hhx_store_hit;
jj_sendExclusiveUnblock; jj_sendExclusiveUnblock;
s_deallocateTBE; s_deallocateTBE;
o_popIncomingResponseQueue; o_popIncomingResponseQueue;
@ -1311,7 +1332,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
transition(SM, Ack_all, M) { transition(SM, Ack_all, M) {
jj_sendExclusiveUnblock; jj_sendExclusiveUnblock;
hh_store_hit; hhx_store_hit;
s_deallocateTBE; s_deallocateTBE;
o_popIncomingResponseQueue; o_popIncomingResponseQueue;
kd_wakeUpDependents; kd_wakeUpDependents;