SE/FS: Expose the same methods on the CPUs in SE and FS modes.
This commit is contained in:
parent
eeb85a8575
commit
1268e0df1f
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@ -47,6 +47,7 @@
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "debug/SyscallVerbose.hh"
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#include "debug/SyscallVerbose.hh"
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#include "params/BaseCPU.hh"
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#include "params/BaseCPU.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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#include "sim/process.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_exit.hh"
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#include "sim/sim_exit.hh"
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@ -197,11 +198,13 @@ BaseCPU::BaseCPU(Params *p)
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}
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}
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interrupts->setCPU(this);
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interrupts->setCPU(this);
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if (FullSystem) {
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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profileEvent = NULL;
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profileEvent = NULL;
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if (params()->profile)
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if (params()->profile)
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profileEvent = new ProfileEvent(this, params()->profile);
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profileEvent = new ProfileEvent(this, params()->profile);
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#endif
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#endif
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}
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tracer = params()->tracer;
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tracer = params()->tracer;
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}
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}
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@ -225,10 +228,10 @@ BaseCPU::init()
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void
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void
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BaseCPU::startup()
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BaseCPU::startup()
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{
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{
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#if FULL_SYSTEM
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if (FullSystem) {
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if (!params()->defer_registration && profileEvent)
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if (!params()->defer_registration && profileEvent)
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schedule(profileEvent, curTick());
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schedule(profileEvent, curTick());
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#endif
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}
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if (params()->progress_interval) {
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if (params()->progress_interval) {
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Tick num_ticks = ticks(params()->progress_interval);
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Tick num_ticks = ticks(params()->progress_interval);
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@ -268,9 +271,6 @@ BaseCPU::regStats()
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}
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}
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} else if (size == 1)
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} else if (size == 1)
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threadContexts[0]->regStats(name());
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threadContexts[0]->regStats(name());
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#if FULL_SYSTEM
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#endif
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}
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}
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Tick
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Tick
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@ -312,9 +312,9 @@ BaseCPU::registerThreadContexts()
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tc->setContextId(system->registerThreadContext(tc, _cpuId));
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tc->setContextId(system->registerThreadContext(tc, _cpuId));
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else
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else
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tc->setContextId(system->registerThreadContext(tc));
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tc->setContextId(system->registerThreadContext(tc));
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#if !FULL_SYSTEM
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tc->getProcessPtr()->assignThreadContext(tc->contextId());
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if (!FullSystem)
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#endif
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tc->getProcessPtr()->assignThreadContext(tc->contextId());
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}
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}
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}
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}
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@ -333,11 +333,8 @@ BaseCPU::findContext(ThreadContext *tc)
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void
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void
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BaseCPU::switchOut()
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BaseCPU::switchOut()
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{
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{
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// panic("This CPU doesn't support sampling!");
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#if FULL_SYSTEM
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if (profileEvent && profileEvent->scheduled())
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if (profileEvent && profileEvent->scheduled())
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deschedule(profileEvent);
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deschedule(profileEvent);
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#endif
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}
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}
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void
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void
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@ -391,13 +388,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
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interrupts = oldCPU->interrupts;
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interrupts = oldCPU->interrupts;
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interrupts->setCPU(this);
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interrupts->setCPU(this);
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#if FULL_SYSTEM
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if (FullSystem) {
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for (ThreadID i = 0; i < size; ++i)
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for (ThreadID i = 0; i < size; ++i)
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threadContexts[i]->profileClear();
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threadContexts[i]->profileClear();
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if (profileEvent)
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if (profileEvent)
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schedule(profileEvent, curTick());
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schedule(profileEvent, curTick());
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#endif
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}
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// Connect new CPU to old CPU's memory only if new CPU isn't
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// Connect new CPU to old CPU's memory only if new CPU isn't
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// connected to anything. Also connect old CPU's memory to new
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// connected to anything. Also connect old CPU's memory to new
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@ -416,7 +413,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
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}
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}
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#if FULL_SYSTEM
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BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
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BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
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: cpu(_cpu), interval(_interval)
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: cpu(_cpu), interval(_interval)
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{ }
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{ }
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@ -433,8 +429,6 @@ BaseCPU::ProfileEvent::process()
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cpu->schedule(this, curTick() + interval);
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cpu->schedule(this, curTick() + interval);
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}
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}
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#endif // FULL_SYSTEM
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void
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void
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BaseCPU::serialize(std::ostream &os)
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BaseCPU::serialize(std::ostream &os)
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{
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{
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@ -44,6 +44,7 @@
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#include "config/the_isa.hh"
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#include "config/the_isa.hh"
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#include "mem/mem_object.hh"
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#include "mem/mem_object.hh"
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#include "sim/eventq.hh"
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#include "sim/eventq.hh"
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#include "sim/full_system.hh"
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#include "sim/insttracer.hh"
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#include "sim/insttracer.hh"
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class BaseCPUParams;
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class BaseCPUParams;
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@ -132,17 +133,14 @@ class BaseCPU : public MemObject
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return interrupts;
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return interrupts;
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}
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}
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#if FULL_SYSTEM
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virtual void wakeup() = 0;
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virtual void wakeup() = 0;
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#endif
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void
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void
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postInterrupt(int int_num, int index)
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postInterrupt(int int_num, int index)
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{
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{
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interrupts->post(int_num, index);
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interrupts->post(int_num, index);
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#if FULL_SYSTEM
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if (FullSystem)
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wakeup();
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wakeup();
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#endif
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}
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}
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void
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void
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@ -111,7 +111,6 @@ class ExecContext {
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Fault writeMem(uint8_t *data, unsigned size,
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Fault writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res);
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Addr addr, unsigned flags, uint64_t *res);
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#if FULL_SYSTEM
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/** Somewhat Alpha-specific function that handles returning from
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/** Somewhat Alpha-specific function that handles returning from
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* an error or interrupt. */
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* an error or interrupt. */
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Fault hwrei();
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Fault hwrei();
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@ -121,10 +120,9 @@ class ExecContext {
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* return value is false, actual PAL call will be suppressed.
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* return value is false, actual PAL call will be suppressed.
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*/
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*/
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bool simPalCheck(int palFunc);
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bool simPalCheck(int palFunc);
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#else
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/** Executes a syscall specified by the callnum. */
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/** Executes a syscall specified by the callnum. */
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void syscall(int64_t callnum);
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void syscall(int64_t callnum);
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#endif
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/** Finish a DTB address translation. */
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/** Finish a DTB address translation. */
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void finishTranslation(WholeTranslationState *state);
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void finishTranslation(WholeTranslationState *state);
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@ -1688,7 +1688,6 @@ InOrderCPU::wakeCPU()
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schedule(&tickEvent, nextCycle(curTick()));
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schedule(&tickEvent, nextCycle(curTick()));
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}
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}
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#if FULL_SYSTEM
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// Lots of copied full system code...place into BaseCPU class?
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// Lots of copied full system code...place into BaseCPU class?
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void
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void
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InOrderCPU::wakeup()
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InOrderCPU::wakeup()
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DPRINTF(Quiesce, "Suspended Processor woken\n");
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DPRINTF(Quiesce, "Suspended Processor woken\n");
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threadContexts[0]->activate();
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threadContexts[0]->activate();
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}
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}
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#endif
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void
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void
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InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
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InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
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@ -751,9 +751,7 @@ class InOrderCPU : public BaseCPU
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/** Wakes the CPU, rescheduling the CPU if it's not already active. */
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/** Wakes the CPU, rescheduling the CPU if it's not already active. */
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void wakeCPU();
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void wakeCPU();
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#if FULL_SYSTEM
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virtual void wakeup();
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virtual void wakeup();
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#endif
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/* LL/SC debug functionality
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/* LL/SC debug functionality
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unsigned stCondFails;
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unsigned stCondFails;
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#include "cpu/exetrace.hh"
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#include "cpu/exetrace.hh"
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#include "debug/InOrderDynInst.hh"
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#include "debug/InOrderDynInst.hh"
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#include "mem/request.hh"
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#include "mem/request.hh"
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#include "sim/full_system.hh"
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using namespace std;
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using namespace std;
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using namespace TheISA;
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using namespace TheISA;
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}
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}
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#if FULL_SYSTEM
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Fault
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Fault
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InOrderDynInst::hwrei()
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InOrderDynInst::hwrei()
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{
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{
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#endif
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#endif
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return this->cpu->simPalCheck(palFunc, this->threadNumber);
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return this->cpu->simPalCheck(palFunc, this->threadNumber);
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}
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}
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#endif
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void
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void
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InOrderDynInst::syscall(int64_t callnum)
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InOrderDynInst::syscall(int64_t callnum)
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{
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{
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#if FULL_SYSTEM
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if (FullSystem) {
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panic("Syscall emulation isn't available in FS mode.\n");
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panic("Syscall emulation isn't available in FS mode.\n");
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#else
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} else {
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syscallNum = callnum;
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syscallNum = callnum;
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cpu->syscallContext(NoFault, this->threadNumber, this);
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cpu->syscallContext(NoFault, this->threadNumber, this);
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#endif
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}
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}
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}
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void
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void
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@ -517,15 +517,12 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
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void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
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/** Calls a syscall. */
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/** Calls a syscall. */
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#if FULL_SYSTEM
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/** Calls hardware return from error interrupt. */
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/** Calls hardware return from error interrupt. */
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Fault hwrei();
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Fault hwrei();
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/** Traps to handle specified fault. */
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/** Traps to handle specified fault. */
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void trap(Fault fault);
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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bool simPalCheck(int palFunc);
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#else
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short syscallNum;
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short syscallNum;
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#endif
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/** Emulates a syscall. */
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/** Emulates a syscall. */
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void syscall(int64_t callnum);
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void syscall(int64_t callnum);
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* Rick Strong
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* Rick Strong
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*/
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*/
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#include "arch/kernel_stats.hh"
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#include "config/full_system.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#include "config/the_isa.hh"
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#include "config/use_checker.hh"
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#include "config/use_checker.hh"
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@ -38,6 +39,7 @@
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#include "cpu/o3/isa_specific.hh"
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#include "cpu/o3/isa_specific.hh"
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#include "cpu/o3/thread_context.hh"
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#include "cpu/o3/thread_context.hh"
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#include "cpu/activity.hh"
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#include "cpu/activity.hh"
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#include "cpu/quiesce_event.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Activity.hh"
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#include "debug/Activity.hh"
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#include "debug/Quiesce.hh"
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#include "debug/Quiesce.hh"
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#include "enums/MemoryMode.hh"
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#include "enums/MemoryMode.hh"
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#include "sim/core.hh"
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#include "sim/core.hh"
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#include "sim/process.hh"
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#include "sim/stat_control.hh"
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#include "sim/stat_control.hh"
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#include "sim/system.hh"
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#include "sim/system.hh"
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#if FULL_SYSTEM
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#include "cpu/quiesce_event.hh"
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#else
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#include "sim/process.hh"
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#endif
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#if USE_CHECKER
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#if USE_CHECKER
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#include "cpu/checker/cpu.hh"
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#include "cpu/checker/cpu.hh"
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#endif
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#endif
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@ -896,7 +893,6 @@ FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
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}
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}
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}
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}
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#if FULL_SYSTEM
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template <class Impl>
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template <class Impl>
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Fault
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Fault
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FullO3CPU<Impl>::hwrei(ThreadID tid)
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FullO3CPU<Impl>::hwrei(ThreadID tid)
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@ -973,7 +969,6 @@ FullO3CPU<Impl>::updateMemPorts()
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for (ThreadID i = 0; i < size; ++i)
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for (ThreadID i = 0; i < size; ++i)
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thread[i]->connectMemPorts(thread[i]->getTC());
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thread[i]->connectMemPorts(thread[i]->getTC());
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}
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}
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#endif
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template <class Impl>
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template <class Impl>
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void
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void
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schedule(tickEvent, nextCycle());
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schedule(tickEvent, nextCycle());
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}
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}
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#if FULL_SYSTEM
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template <class Impl>
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template <class Impl>
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void
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void
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FullO3CPU<Impl>::wakeup()
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FullO3CPU<Impl>::wakeup()
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DPRINTF(Quiesce, "Suspended Processor woken\n");
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DPRINTF(Quiesce, "Suspended Processor woken\n");
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this->threadContexts[0]->activate();
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this->threadContexts[0]->activate();
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}
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}
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#endif
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template <class Impl>
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template <class Impl>
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ThreadID
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ThreadID
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/** Traps to handle given fault. */
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/** Traps to handle given fault. */
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void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
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void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
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#if FULL_SYSTEM
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/** HW return from error interrupt. */
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/** HW return from error interrupt. */
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Fault hwrei(ThreadID tid);
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Fault hwrei(ThreadID tid);
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@ -402,7 +401,6 @@ class FullO3CPU : public BaseO3CPU
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/** Check if this address is a valid data address. */
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/** Check if this address is a valid data address. */
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bool validDataAddr(Addr addr) { return true; }
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bool validDataAddr(Addr addr) { return true; }
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#endif
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/** Register accessors. Index refers to the physical register index. */
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/** Register accessors. Index refers to the physical register index. */
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@ -631,9 +629,7 @@ class FullO3CPU : public BaseO3CPU
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/** Wakes the CPU, rescheduling the CPU if it's not already active. */
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/** Wakes the CPU, rescheduling the CPU if it's not already active. */
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void wakeCPU();
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void wakeCPU();
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#if FULL_SYSTEM
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virtual void wakeup();
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virtual void wakeup();
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#endif
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/** Gets a free thread id. Use if thread ids change across system. */
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/** Gets a free thread id. Use if thread ids change across system. */
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ThreadID getFreeTid();
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ThreadID getFreeTid();
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@ -199,13 +199,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
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this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
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this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
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}
|
}
|
||||||
}
|
}
|
||||||
#if FULL_SYSTEM
|
|
||||||
/** Calls hardware return from error interrupt. */
|
/** Calls hardware return from error interrupt. */
|
||||||
Fault hwrei();
|
Fault hwrei();
|
||||||
/** Traps to handle specified fault. */
|
/** Traps to handle specified fault. */
|
||||||
void trap(Fault fault);
|
void trap(Fault fault);
|
||||||
bool simPalCheck(int palFunc);
|
bool simPalCheck(int palFunc);
|
||||||
#endif
|
|
||||||
|
|
||||||
/** Emulates a syscall. */
|
/** Emulates a syscall. */
|
||||||
void syscall(int64_t callnum);
|
void syscall(int64_t callnum);
|
||||||
|
|
|
@ -42,6 +42,7 @@
|
||||||
|
|
||||||
#include "base/cp_annotate.hh"
|
#include "base/cp_annotate.hh"
|
||||||
#include "cpu/o3/dyn_inst.hh"
|
#include "cpu/o3/dyn_inst.hh"
|
||||||
|
#include "sim/full_system.hh"
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
|
BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
|
||||||
|
@ -143,7 +144,6 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
|
||||||
return this->fault;
|
return this->fault;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
Fault
|
Fault
|
||||||
BaseO3DynInst<Impl>::hwrei()
|
BaseO3DynInst<Impl>::hwrei()
|
||||||
|
@ -188,24 +188,23 @@ BaseO3DynInst<Impl>::simPalCheck(int palFunc)
|
||||||
#endif
|
#endif
|
||||||
return this->cpu->simPalCheck(palFunc, this->threadNumber);
|
return this->cpu->simPalCheck(palFunc, this->threadNumber);
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
BaseO3DynInst<Impl>::syscall(int64_t callnum)
|
BaseO3DynInst<Impl>::syscall(int64_t callnum)
|
||||||
{
|
{
|
||||||
#if FULL_SYSTEM
|
if (FullSystem) {
|
||||||
panic("Syscall emulation isn't available in FS mode.\n");
|
panic("Syscall emulation isn't available in FS mode.\n");
|
||||||
#else
|
} else {
|
||||||
// HACK: check CPU's nextPC before and after syscall. If it
|
// HACK: check CPU's nextPC before and after syscall. If it
|
||||||
// changes, update this instruction's nextPC because the syscall
|
// changes, update this instruction's nextPC because the syscall
|
||||||
// must have changed the nextPC.
|
// must have changed the nextPC.
|
||||||
TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
|
TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
|
||||||
this->cpu->syscall(callnum, this->threadNumber);
|
this->cpu->syscall(callnum, this->threadNumber);
|
||||||
TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
|
TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
|
||||||
if (!(curPC == newPC)) {
|
if (!(curPC == newPC)) {
|
||||||
this->pcState(newPC);
|
this->pcState(newPC);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,7 @@
|
||||||
#include "params/AtomicSimpleCPU.hh"
|
#include "params/AtomicSimpleCPU.hh"
|
||||||
#include "sim/faults.hh"
|
#include "sim/faults.hh"
|
||||||
#include "sim/system.hh"
|
#include "sim/system.hh"
|
||||||
|
#include "sim/full_system.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
using namespace TheISA;
|
using namespace TheISA;
|
||||||
|
@ -83,15 +84,16 @@ void
|
||||||
AtomicSimpleCPU::init()
|
AtomicSimpleCPU::init()
|
||||||
{
|
{
|
||||||
BaseCPU::init();
|
BaseCPU::init();
|
||||||
|
if (FullSystem) {
|
||||||
|
ThreadID size = threadContexts.size();
|
||||||
|
for (ThreadID i = 0; i < size; ++i) {
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
ThreadID size = threadContexts.size();
|
ThreadContext *tc = threadContexts[i];
|
||||||
for (ThreadID i = 0; i < size; ++i) {
|
// initialize CPU, including PC
|
||||||
ThreadContext *tc = threadContexts[i];
|
TheISA::initCPU(tc, tc->contextId());
|
||||||
|
|
||||||
// initialize CPU, including PC
|
|
||||||
TheISA::initCPU(tc, tc->contextId());
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
if (hasPhysMemPort) {
|
if (hasPhysMemPort) {
|
||||||
bool snoop = false;
|
bool snoop = false;
|
||||||
AddrRangeList pmAddrList;
|
AddrRangeList pmAddrList;
|
||||||
|
@ -150,11 +152,11 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
|
||||||
{
|
{
|
||||||
Port::setPeer(port);
|
Port::setPeer(port);
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
if (FullSystem) {
|
||||||
// Update the ThreadContext's memory ports (Functional/Virtual
|
// Update the ThreadContext's memory ports (Functional/Virtual
|
||||||
// Ports)
|
// Ports)
|
||||||
cpu->tcBase()->connectMemPorts(cpu->tcBase());
|
cpu->tcBase()->connectMemPorts(cpu->tcBase());
|
||||||
#endif
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
|
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
|
||||||
|
@ -617,7 +619,7 @@ AtomicSimpleCPUParams::create()
|
||||||
{
|
{
|
||||||
numThreads = 1;
|
numThreads = 1;
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
if (workload.size() != 1)
|
if (!FullSystem && workload.size() != 1)
|
||||||
panic("only one workload allowed");
|
panic("only one workload allowed");
|
||||||
#endif
|
#endif
|
||||||
return new AtomicSimpleCPU(this);
|
return new AtomicSimpleCPU(this);
|
||||||
|
|
|
@ -41,7 +41,11 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "arch/faults.hh"
|
#include "arch/faults.hh"
|
||||||
|
#include "arch/kernel_stats.hh"
|
||||||
|
#include "arch/stacktrace.hh"
|
||||||
|
#include "arch/tlb.hh"
|
||||||
#include "arch/utility.hh"
|
#include "arch/utility.hh"
|
||||||
|
#include "arch/vtophys.hh"
|
||||||
#include "base/loader/symtab.hh"
|
#include "base/loader/symtab.hh"
|
||||||
#include "base/cp_annotate.hh"
|
#include "base/cp_annotate.hh"
|
||||||
#include "base/cprintf.hh"
|
#include "base/cprintf.hh"
|
||||||
|
@ -63,6 +67,7 @@
|
||||||
#include "debug/Decode.hh"
|
#include "debug/Decode.hh"
|
||||||
#include "debug/Fetch.hh"
|
#include "debug/Fetch.hh"
|
||||||
#include "debug/Quiesce.hh"
|
#include "debug/Quiesce.hh"
|
||||||
|
#include "mem/mem_object.hh"
|
||||||
#include "mem/packet.hh"
|
#include "mem/packet.hh"
|
||||||
#include "mem/request.hh"
|
#include "mem/request.hh"
|
||||||
#include "params/BaseSimpleCPU.hh"
|
#include "params/BaseSimpleCPU.hh"
|
||||||
|
@ -73,15 +78,6 @@
|
||||||
#include "sim/stats.hh"
|
#include "sim/stats.hh"
|
||||||
#include "sim/system.hh"
|
#include "sim/system.hh"
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
#include "arch/kernel_stats.hh"
|
|
||||||
#include "arch/stacktrace.hh"
|
|
||||||
#include "arch/tlb.hh"
|
|
||||||
#include "arch/vtophys.hh"
|
|
||||||
#else // !FULL_SYSTEM
|
|
||||||
#include "mem/mem_object.hh"
|
|
||||||
#endif // FULL_SYSTEM
|
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
using namespace TheISA;
|
using namespace TheISA;
|
||||||
|
|
||||||
|
@ -290,15 +286,12 @@ change_thread_state(ThreadID tid, int activate, int priority)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
Addr
|
Addr
|
||||||
BaseSimpleCPU::dbg_vtophys(Addr addr)
|
BaseSimpleCPU::dbg_vtophys(Addr addr)
|
||||||
{
|
{
|
||||||
return vtophys(tc, addr);
|
return vtophys(tc, addr);
|
||||||
}
|
}
|
||||||
#endif // FULL_SYSTEM
|
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void
|
void
|
||||||
BaseSimpleCPU::wakeup()
|
BaseSimpleCPU::wakeup()
|
||||||
{
|
{
|
||||||
|
@ -308,12 +301,10 @@ BaseSimpleCPU::wakeup()
|
||||||
DPRINTF(Quiesce,"Suspended Processor awoke\n");
|
DPRINTF(Quiesce,"Suspended Processor awoke\n");
|
||||||
thread->activate();
|
thread->activate();
|
||||||
}
|
}
|
||||||
#endif // FULL_SYSTEM
|
|
||||||
|
|
||||||
void
|
void
|
||||||
BaseSimpleCPU::checkForInterrupts()
|
BaseSimpleCPU::checkForInterrupts()
|
||||||
{
|
{
|
||||||
#if FULL_SYSTEM
|
|
||||||
if (checkInterrupts(tc)) {
|
if (checkInterrupts(tc)) {
|
||||||
Fault interrupt = interrupts->getInterrupt(tc);
|
Fault interrupt = interrupts->getInterrupt(tc);
|
||||||
|
|
||||||
|
@ -324,7 +315,6 @@ BaseSimpleCPU::checkForInterrupts()
|
||||||
predecoder.reset();
|
predecoder.reset();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -422,7 +412,6 @@ BaseSimpleCPU::postExecute()
|
||||||
|
|
||||||
TheISA::PCState pc = tc->pcState();
|
TheISA::PCState pc = tc->pcState();
|
||||||
Addr instAddr = pc.instAddr();
|
Addr instAddr = pc.instAddr();
|
||||||
#if FULL_SYSTEM
|
|
||||||
if (thread->profile) {
|
if (thread->profile) {
|
||||||
bool usermode = TheISA::inUserMode(tc);
|
bool usermode = TheISA::inUserMode(tc);
|
||||||
thread->profilePC = usermode ? 1 : instAddr;
|
thread->profilePC = usermode ? 1 : instAddr;
|
||||||
|
@ -430,7 +419,6 @@ BaseSimpleCPU::postExecute()
|
||||||
if (node)
|
if (node)
|
||||||
thread->profileNode = node;
|
thread->profileNode = node;
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
if (curStaticInst->isMemRef()) {
|
if (curStaticInst->isMemRef()) {
|
||||||
numMemRefs++;
|
numMemRefs++;
|
||||||
|
|
|
@ -35,7 +35,6 @@
|
||||||
|
|
||||||
#include "arch/predecoder.hh"
|
#include "arch/predecoder.hh"
|
||||||
#include "base/statistics.hh"
|
#include "base/statistics.hh"
|
||||||
#include "config/full_system.hh"
|
|
||||||
#include "config/the_isa.hh"
|
#include "config/the_isa.hh"
|
||||||
#include "cpu/base.hh"
|
#include "cpu/base.hh"
|
||||||
#include "cpu/decode.hh"
|
#include "cpu/decode.hh"
|
||||||
|
@ -46,30 +45,22 @@
|
||||||
#include "mem/port.hh"
|
#include "mem/port.hh"
|
||||||
#include "mem/request.hh"
|
#include "mem/request.hh"
|
||||||
#include "sim/eventq.hh"
|
#include "sim/eventq.hh"
|
||||||
|
#include "sim/full_system.hh"
|
||||||
#include "sim/system.hh"
|
#include "sim/system.hh"
|
||||||
|
|
||||||
// forward declarations
|
// forward declarations
|
||||||
#if FULL_SYSTEM
|
class Checkpoint;
|
||||||
class Processor;
|
|
||||||
namespace TheISA
|
|
||||||
{
|
|
||||||
class ITB;
|
|
||||||
class DTB;
|
|
||||||
}
|
|
||||||
class MemObject;
|
class MemObject;
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
class Process;
|
class Process;
|
||||||
|
class Processor;
|
||||||
#endif // FULL_SYSTEM
|
class ThreadContext;
|
||||||
|
|
||||||
namespace TheISA
|
namespace TheISA
|
||||||
{
|
{
|
||||||
|
class DTB;
|
||||||
|
class ITB;
|
||||||
class Predecoder;
|
class Predecoder;
|
||||||
}
|
}
|
||||||
class ThreadContext;
|
|
||||||
class Checkpoint;
|
|
||||||
|
|
||||||
namespace Trace {
|
namespace Trace {
|
||||||
class InstRecord;
|
class InstRecord;
|
||||||
|
@ -141,11 +132,9 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
Addr dbg_vtophys(Addr addr);
|
Addr dbg_vtophys(Addr addr);
|
||||||
|
|
||||||
bool interval_stats;
|
bool interval_stats;
|
||||||
#endif
|
|
||||||
|
|
||||||
// current instruction
|
// current instruction
|
||||||
TheISA::MachInst inst;
|
TheISA::MachInst inst;
|
||||||
|
@ -399,19 +388,16 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
|
|
||||||
//Fault CacheOp(uint8_t Op, Addr EA);
|
//Fault CacheOp(uint8_t Op, Addr EA);
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
Fault hwrei() { return thread->hwrei(); }
|
Fault hwrei() { return thread->hwrei(); }
|
||||||
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
|
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
|
||||||
#endif
|
|
||||||
|
|
||||||
void
|
void
|
||||||
syscall(int64_t callnum)
|
syscall(int64_t callnum)
|
||||||
{
|
{
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
panic("Syscall emulation isn't available in FS mode.\n");
|
panic("Syscall emulation isn't available in FS mode.\n");
|
||||||
#else
|
else
|
||||||
thread->syscall(callnum);
|
thread->syscall(callnum);
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
bool misspeculating() { return thread->misspeculating(); }
|
bool misspeculating() { return thread->misspeculating(); }
|
||||||
|
|
|
@ -54,6 +54,7 @@
|
||||||
#include "mem/packet_access.hh"
|
#include "mem/packet_access.hh"
|
||||||
#include "params/TimingSimpleCPU.hh"
|
#include "params/TimingSimpleCPU.hh"
|
||||||
#include "sim/faults.hh"
|
#include "sim/faults.hh"
|
||||||
|
#include "sim/full_system.hh"
|
||||||
#include "sim/system.hh"
|
#include "sim/system.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
@ -74,14 +75,15 @@ void
|
||||||
TimingSimpleCPU::init()
|
TimingSimpleCPU::init()
|
||||||
{
|
{
|
||||||
BaseCPU::init();
|
BaseCPU::init();
|
||||||
|
if (FullSystem) {
|
||||||
|
for (int i = 0; i < threadContexts.size(); ++i) {
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
for (int i = 0; i < threadContexts.size(); ++i) {
|
ThreadContext *tc = threadContexts[i];
|
||||||
ThreadContext *tc = threadContexts[i];
|
// initialize CPU, including PC
|
||||||
|
TheISA::initCPU(tc, _cpuId);
|
||||||
// initialize CPU, including PC
|
|
||||||
TheISA::initCPU(tc, _cpuId);
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
Tick
|
Tick
|
||||||
|
@ -879,11 +881,11 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port)
|
||||||
{
|
{
|
||||||
Port::setPeer(port);
|
Port::setPeer(port);
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
if (FullSystem) {
|
||||||
// Update the ThreadContext's memory ports (Functional/Virtual
|
// Update the ThreadContext's memory ports (Functional/Virtual
|
||||||
// Ports)
|
// Ports)
|
||||||
cpu->tcBase()->connectMemPorts(cpu->tcBase());
|
cpu->tcBase()->connectMemPorts(cpu->tcBase());
|
||||||
#endif
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
|
@ -1008,7 +1010,7 @@ TimingSimpleCPUParams::create()
|
||||||
{
|
{
|
||||||
numThreads = 1;
|
numThreads = 1;
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
if (workload.size() != 1)
|
if (!FullSystem && workload.size() != 1)
|
||||||
panic("only one workload allowed");
|
panic("only one workload allowed");
|
||||||
#endif
|
#endif
|
||||||
return new TimingSimpleCPU(this);
|
return new TimingSimpleCPU(this);
|
||||||
|
|
Loading…
Reference in a new issue