diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index 541bdbd83..ad2d1b87b 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -29,15 +29,15 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-class OpType(Enum):
-    vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
+class OpClass(Enum):
+    vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
             'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
             'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
 
 class OpDesc(SimObject):
     type = 'OpDesc'
     issueLat = Param.Int(1, "cycles until another can be issued")
-    opClass = Param.OpType("type of operation")
+    opClass = Param.OpClass("type of operation")
     opLat = Param.Int(1, "cycles until result is available")
 
 class FUDesc(SimObject):
diff --git a/src/cpu/op_class.cc b/src/cpu/op_class.cc
index f7ef49c0f..02cb4a08a 100644
--- a/src/cpu/op_class.cc
+++ b/src/cpu/op_class.cc
@@ -34,7 +34,7 @@
 const char *
 opClassStrings[Num_OpClasses] =
 {
-    "(null)",
+    "No_OpClass",
     "IntAlu",
     "IntMult",
     "IntDiv",