O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.
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62f2097917
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11bef2ab38
2 changed files with 42 additions and 31 deletions
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@ -452,20 +452,24 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
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DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
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"[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
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if (toCommit->squash[tid] == false ||
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inst->seqNum < toCommit->squashedSeqNum[tid]) {
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toCommit->squash[tid] = true;
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toCommit->squashedSeqNum[tid] = inst->seqNum;
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toCommit->mispredPC[tid] = inst->instAddr();
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toCommit->branchMispredict[tid] = true;
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toCommit->mispredictInst[tid] = inst;
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toCommit->branchTaken[tid] = inst->pcState().branching();
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TheISA::PCState pc = inst->pcState();
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TheISA::advancePC(pc, inst->staticInst);
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toCommit->pc[tid] = pc;
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toCommit->pc[tid] = pc;
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toCommit->mispredictInst[tid] = inst;
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toCommit->includeSquashInst[tid] = false;
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wroteToTimeBuffer = true;
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}
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}
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template<class Impl>
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@ -475,6 +479,8 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
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DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
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"PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
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if (toCommit->squash[tid] == false ||
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inst->seqNum < toCommit->squashedSeqNum[tid]) {
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toCommit->squash[tid] = true;
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toCommit->squashedSeqNum[tid] = inst->seqNum;
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TheISA::PCState pc = inst->pcState();
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@ -485,6 +491,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
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toCommit->includeSquashInst[tid] = false;
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wroteToTimeBuffer = true;
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}
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}
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template<class Impl>
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@ -493,8 +500,10 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
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{
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DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
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"PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
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if (toCommit->squash[tid] == false ||
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inst->seqNum < toCommit->squashedSeqNum[tid]) {
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toCommit->squash[tid] = true;
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toCommit->squashedSeqNum[tid] = inst->seqNum;
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toCommit->pc[tid] = inst->pcState();
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toCommit->branchMispredict[tid] = false;
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@ -505,6 +514,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
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ldstQueue.setLoadBlockedHandled(tid);
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wroteToTimeBuffer = true;
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}
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}
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template<class Impl>
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@ -788,7 +798,6 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
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}
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dispatchStatus[tid] = Squashing;
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fetchRedirect[tid] = false;
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return;
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}
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@ -797,7 +806,6 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
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DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
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dispatchStatus[tid] = Squashing;
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emptyRenameInsts(tid);
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wroteToTimeBuffer = true;
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return;
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@ -1286,6 +1294,7 @@ DefaultIEW<Impl>::executeInsts()
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ThreadID tid = inst->threadNumber;
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if (!fetchRedirect[tid] ||
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!toCommit->squash[tid] ||
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toCommit->squashedSeqNum[tid] > inst->seqNum) {
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if (inst->mispredicted()) {
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@ -1382,6 +1391,7 @@ DefaultIEW<Impl>::executeInsts()
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// iew queue. That way the writeback event will write into the correct
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// spot in the queue.
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wbNumInst = 0;
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}
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template <class Impl>
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@ -1596,6 +1606,7 @@ DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
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ThreadID tid = inst->threadNumber;
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if (!fetchRedirect[tid] ||
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!toCommit->squash[tid] ||
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toCommit->squashedSeqNum[tid] > inst->seqNum) {
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if (inst->mispredicted()) {
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@ -90,8 +90,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
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{
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LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
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DynInstPtr inst = state->inst;
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DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
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DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
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DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
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DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
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//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
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