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O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.

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This commit is contained in:
Matt Horsnell 2011-01-18 16:30:05 -06:00
parent 62f2097917
commit 11bef2ab38
2 changed files with 42 additions and 31 deletions
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23
src/cpu/o3/iew_impl.hh
View file

@ -452,20 +452,24 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
"[sn:%i].\n", tid, inst->pcState(), inst->seqNum); "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
if (toCommit->squash[tid] == false ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true; toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->mispredPC[tid] = inst->instAddr(); toCommit->mispredPC[tid] = inst->instAddr();
toCommit->branchMispredict[tid] = true; toCommit->branchMispredict[tid] = true;
toCommit->mispredictInst[tid] = inst;
toCommit->branchTaken[tid] = inst->pcState().branching(); toCommit->branchTaken[tid] = inst->pcState().branching();
TheISA::PCState pc = inst->pcState(); TheISA::PCState pc = inst->pcState();
TheISA::advancePC(pc, inst->staticInst); TheISA::advancePC(pc, inst->staticInst);
toCommit->pc[tid] = pc;
toCommit->pc[tid] = pc;
toCommit->mispredictInst[tid] = inst;
toCommit->includeSquashInst[tid] = false; toCommit->includeSquashInst[tid] = false;
wroteToTimeBuffer = true; wroteToTimeBuffer = true;
}
} }
template<class Impl> template<class Impl>
@ -475,6 +479,8 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
"PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
if (toCommit->squash[tid] == false ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true; toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->squashedSeqNum[tid] = inst->seqNum;
TheISA::PCState pc = inst->pcState(); TheISA::PCState pc = inst->pcState();
@ -485,6 +491,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
toCommit->includeSquashInst[tid] = false; toCommit->includeSquashInst[tid] = false;
wroteToTimeBuffer = true; wroteToTimeBuffer = true;
}
} }
template<class Impl> template<class Impl>
@ -493,8 +500,10 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
{ {
DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
"PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
if (toCommit->squash[tid] == false ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true; toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->pc[tid] = inst->pcState(); toCommit->pc[tid] = inst->pcState();
toCommit->branchMispredict[tid] = false; toCommit->branchMispredict[tid] = false;
@ -505,6 +514,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
ldstQueue.setLoadBlockedHandled(tid); ldstQueue.setLoadBlockedHandled(tid);
wroteToTimeBuffer = true; wroteToTimeBuffer = true;
}
} }
template<class Impl> template<class Impl>
@ -788,7 +798,6 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
} }
dispatchStatus[tid] = Squashing; dispatchStatus[tid] = Squashing;
fetchRedirect[tid] = false; fetchRedirect[tid] = false;
return; return;
} }
@ -797,7 +806,6 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
dispatchStatus[tid] = Squashing; dispatchStatus[tid] = Squashing;
emptyRenameInsts(tid); emptyRenameInsts(tid);
wroteToTimeBuffer = true; wroteToTimeBuffer = true;
return; return;
@ -1286,6 +1294,7 @@ DefaultIEW<Impl>::executeInsts()
ThreadID tid = inst->threadNumber; ThreadID tid = inst->threadNumber;
if (!fetchRedirect[tid] || if (!fetchRedirect[tid] ||
!toCommit->squash[tid] ||
toCommit->squashedSeqNum[tid] > inst->seqNum) { toCommit->squashedSeqNum[tid] > inst->seqNum) {
if (inst->mispredicted()) { if (inst->mispredicted()) {
@ -1382,6 +1391,7 @@ DefaultIEW<Impl>::executeInsts()
// iew queue. That way the writeback event will write into the correct // iew queue. That way the writeback event will write into the correct
// spot in the queue. // spot in the queue.
wbNumInst = 0; wbNumInst = 0;
} }
template <class Impl> template <class Impl>
@ -1596,6 +1606,7 @@ DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
ThreadID tid = inst->threadNumber; ThreadID tid = inst->threadNumber;
if (!fetchRedirect[tid] || if (!fetchRedirect[tid] ||
!toCommit->squash[tid] ||
toCommit->squashedSeqNum[tid] > inst->seqNum) { toCommit->squashedSeqNum[tid] > inst->seqNum) {
if (inst->mispredicted()) { if (inst->mispredicted()) {

4
src/cpu/o3/lsq_unit_impl.hh
View file

@ -90,8 +90,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
{ {
LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
DynInstPtr inst = state->inst; DynInstPtr inst = state->inst;
DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);