Updates for the quiesceEvent that was added to the XC.
Also several files need to include system.hh or symtab.hh. This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well. arch/alpha/faults.cc: Avoid accessing XC directly. arch/alpha/stacktrace.cc: StackTrace needs to include system.hh. cpu/cpu_exec_context.cc: Update for change to CPUExecContext. cpu/cpu_exec_context.hh: Make quiesce events use CPUExecContext instead of ExecContext. Include functions to allow the quiesce event and last activate/suspend be accessed. cpu/exec_context.hh: Include functions for quiesceEvent. cpu/intr_control.cc: Needs to include cpu/exec_context.hh. cpu/profile.cc: Needs to include symtab.hh for the symbol table. cpu/profile.hh: Needs forward declare of ExecContext. cpu/simple/cpu.cc: Rename xc to cpuXC. dev/tsunami_cchip.cc: Needs to include exec_context.hh. kern/kernel_stats.cc: Needs to include system.hh. kern/linux/events.cc: Needs to include system.hh. Also avoid accessing objects directly from the XC. kern/tru64/dump_mbuf.cc: Include symtab.hh for the SymbolTable and system.hh. kern/tru64/tru64_events.cc: Include system.hh sim/pseudo_inst.cc: Avoid accessing objects directly within the XC. --HG-- extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84
This commit is contained in:
parent
20eced3ea0
commit
11aead894d
15 changed files with 93 additions and 60 deletions
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@ -103,15 +103,15 @@ FaultStat IntegerOverflowFault::_stat;
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void AlphaFault::invoke(ExecContext * xc)
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void AlphaFault::invoke(ExecContext * xc)
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{
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{
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DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
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DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->readPC());
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xc->cpu->recordEvent(csprintf("Fault %s", name()));
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xc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
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assert(!xc->misspeculating());
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assert(!xc->misspeculating());
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xc->kernelStats->fault(this);
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xc->getCpuPtr()->kernelStats->fault(this);
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// exception restart address
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// exception restart address
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if (setRestartAddress() || !xc->inPalMode())
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if (setRestartAddress() || !xc->inPalMode())
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xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
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xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
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if (skipFaultingInstruction()) {
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if (skipFaultingInstruction()) {
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// traps... skip faulting instruction.
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// traps... skip faulting instruction.
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@ -119,17 +119,17 @@ void AlphaFault::invoke(ExecContext * xc)
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xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
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xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
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}
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}
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xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
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xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
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xc->regs.npc = xc->regs.pc + sizeof(MachInst);
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xc->setNextPC(xc->readPC() + sizeof(MachInst));
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}
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}
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void ArithmeticFault::invoke(ExecContext * xc)
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void ArithmeticFault::invoke(ExecContext * xc)
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{
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{
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DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
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DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->readPC());
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xc->cpu->recordEvent(csprintf("Fault %s", name()));
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xc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
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assert(!xc->misspeculating());
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assert(!xc->misspeculating());
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xc->kernelStats->fault(this);
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xc->getCpuPtr()->kernelStats->fault(this);
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panic("Arithmetic traps are unimplemented!");
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panic("Arithmetic traps are unimplemented!");
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}
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}
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@ -35,6 +35,7 @@
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace std;
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using namespace AlphaISA;
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using namespace AlphaISA;
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@ -57,8 +57,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
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: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
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: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
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cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
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cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
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dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
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dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
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fnbin(kernelBinning->fnbin), profile(NULL), quiesceEvent(this),
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profile(NULL), quiesceEvent(this), func_exe_inst(0), storeCondFailures(0)
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func_exe_inst(0), storeCondFailures(0)
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{
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{
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proxy = new ProxyExecContext<CPUExecContext>(this);
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proxy = new ProxyExecContext<CPUExecContext>(this);
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@ -119,21 +118,22 @@ void
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CPUExecContext::dumpFuncProfile()
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CPUExecContext::dumpFuncProfile()
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{
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{
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std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
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std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
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profile->dump(proxy, *os);
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}
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}
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ExecContext::EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
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CPUExecContext::EndQuiesceEvent::EndQuiesceEvent(CPUExecContext *_cpuXC)
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: Event(&mainEventQueue), xc(_xc)
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: Event(&mainEventQueue), cpuXC(_cpuXC)
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{
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{
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}
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}
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void
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void
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ExecContext::EndQuiesceEvent::process()
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CPUExecContext::EndQuiesceEvent::process()
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{
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{
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xc->activate();
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cpuXC->activate();
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}
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}
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const char*
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const char*
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ExecContext::EndQuiesceEvent::description()
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CPUExecContext::EndQuiesceEvent::description()
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{
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{
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return "End Quiesce Event.";
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return "End Quiesce Event.";
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}
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}
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@ -142,25 +142,25 @@ ExecContext::EndQuiesceEvent::description()
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void
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void
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CPUExecContext::takeOverFrom(ExecContext *oldContext)
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CPUExecContext::takeOverFrom(ExecContext *oldContext)
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{
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{
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/*
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// some things should already be set up
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// some things should already be set up
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assert(mem == oldContext->mem);
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assert(mem == oldContext->getMemPtr());
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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assert(system == oldContext->system);
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assert(system == oldContext->getSystemPtr());
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#else
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#else
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assert(process == oldContext->process);
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assert(process == oldContext->getProcessPtr());
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#endif
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#endif
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// copy over functional state
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// copy over functional state
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_status = oldContext->_status;
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_status = oldContext->status();
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regs = oldContext->regs;
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copyArchRegs(oldContext);
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cpu_id = oldContext->cpu_id;
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cpu_id = oldContext->readCpuId();
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func_exe_inst = oldContext->func_exe_inst;
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#if !FULL_SYSTEM
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func_exe_inst = oldContext->readFuncExeInst();
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#endif
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storeCondFailures = 0;
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storeCondFailures = 0;
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oldContext->_status = CPUExecContext::Unallocated;
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oldContext->setStatus(ExecContext::Unallocated);
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*/
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}
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}
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void
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void
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@ -281,6 +281,9 @@ CPUExecContext::copyArchRegs(ExecContext *xc)
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setMiscReg(AlphaISA::Lock_Addr_DepTag,
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setMiscReg(AlphaISA::Lock_Addr_DepTag,
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xc->readMiscReg(AlphaISA::Lock_Addr_DepTag));
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xc->readMiscReg(AlphaISA::Lock_Addr_DepTag));
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// Also need to copy all the IPRs. Probably should just have a copy misc
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// regs function defined on the misc regs.
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// Lastly copy PC/NPC
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// Lastly copy PC/NPC
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setPC(xc->readPC());
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setPC(xc->readPC());
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setNextPC(xc->readNextPC());
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setNextPC(xc->readNextPC());
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@ -139,9 +139,9 @@ class CPUExecContext
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struct EndQuiesceEvent : public Event
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struct EndQuiesceEvent : public Event
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{
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{
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/** A pointer to the execution context that is quiesced */
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/** A pointer to the execution context that is quiesced */
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ExecContext *xc;
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CPUExecContext *cpuXC;
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EndQuiesceEvent(ExecContext *_xc);
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EndQuiesceEvent(CPUExecContext *_cpuXC);
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/** Event process to occur at interrupt*/
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/** Event process to occur at interrupt*/
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virtual void process();
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virtual void process();
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@ -151,6 +151,12 @@ class CPUExecContext
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};
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};
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EndQuiesceEvent quiesceEvent;
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EndQuiesceEvent quiesceEvent;
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Event *getQuiesceEvent() { return &quiesceEvent; }
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Tick readLastActivate() { return lastActivate; }
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Tick readLastSuspend() { return lastSuspend; }
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#else
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#else
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Process *process;
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Process *process;
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@ -42,6 +42,7 @@
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class AlphaDTB;
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class AlphaDTB;
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class AlphaITB;
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class AlphaITB;
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class BaseCPU;
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class BaseCPU;
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class Event;
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class FunctionalMemory;
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class FunctionalMemory;
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class PhysicalMemory;
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class PhysicalMemory;
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class Process;
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class Process;
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@ -102,6 +103,8 @@ class ExecContext
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virtual Status status() const = 0;
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virtual Status status() const = 0;
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virtual void setStatus(Status new_status) = 0;
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/// Set the status to Active. Optional delay indicates number of
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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/// cycles to wait before beginning execution.
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virtual void activate(int delay = 1) = 0;
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virtual void activate(int delay = 1) = 0;
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@ -119,13 +122,22 @@ class ExecContext
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virtual void dumpFuncProfile() = 0;
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virtual void dumpFuncProfile() = 0;
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#endif
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#endif
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virtual void takeOverFrom(ExecContext *oldContext) = 0;
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virtual void takeOverFrom(ExecContext *old_context) = 0;
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virtual void regStats(const std::string &name) = 0;
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virtual void regStats(const std::string &name) = 0;
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virtual void serialize(std::ostream &os) = 0;
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virtual void serialize(std::ostream &os) = 0;
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virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
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virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
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#if FULL_SYSTEM
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virtual Event *getQuiesceEvent() = 0;
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// Not necessarily the best location for these...
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// Having an extra function just to read these is obnoxious
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virtual Tick readLastActivate() = 0;
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virtual Tick readLastSuspend() = 0;
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#endif
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virtual int getThreadNum() = 0;
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virtual int getThreadNum() = 0;
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virtual bool validInstAddr(Addr addr) = 0;
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virtual bool validInstAddr(Addr addr) = 0;
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virtual Fault translateDataWriteReq(MemReqPtr &req) = 0;
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virtual Fault translateDataWriteReq(MemReqPtr &req) = 0;
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// Also somewhat obnoxious. Really only used for the TLB fault.
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virtual TheISA::MachInst getInst() = 0;
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virtual TheISA::MachInst getInst() = 0;
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virtual void copyArchRegs(ExecContext *xc) = 0;
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virtual void copyArchRegs(ExecContext *xc) = 0;
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@ -180,6 +193,8 @@ class ExecContext
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virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
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virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
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// Also not necessarily the best location for these two. Hopefully will go
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// away once we decide upon where st cond failures goes.
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virtual unsigned readStCondFailures() = 0;
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virtual unsigned readStCondFailures() = 0;
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virtual void setStCondFailures(unsigned sc_failures) = 0;
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virtual void setStCondFailures(unsigned sc_failures) = 0;
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@ -189,20 +204,12 @@ class ExecContext
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virtual void setIntrFlag(int val) = 0;
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virtual void setIntrFlag(int val) = 0;
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virtual Fault hwrei() = 0;
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virtual Fault hwrei() = 0;
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virtual bool inPalMode() = 0;
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virtual bool inPalMode() = 0;
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virtual void ev5_trap(Fault fault) = 0;
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virtual bool simPalCheck(int palFunc) = 0;
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virtual bool simPalCheck(int palFunc) = 0;
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#endif
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#endif
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// Only really makes sense for old CPU model. Still could be useful though.
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virtual bool misspeculating() = 0;
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virtual bool misspeculating() = 0;
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/** Meant to be more generic trap function to be
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* called when an instruction faults.
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* @param fault The fault generated by executing the instruction.
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* @todo How to do this properly so it's dependent upon ISA only?
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*/
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virtual void trap(Fault fault) = 0;
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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virtual IntReg getSyscallArg(int i) = 0;
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virtual IntReg getSyscallArg(int i) = 0;
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@ -213,6 +220,7 @@ class ExecContext
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virtual void syscall() = 0;
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virtual void syscall() = 0;
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// Same with st cond failures.
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virtual Counter readFuncExeInst() = 0;
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virtual Counter readFuncExeInst() = 0;
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virtual void setFuncExeInst(Counter new_val) = 0;
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virtual void setFuncExeInst(Counter new_val) = 0;
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@ -253,6 +261,8 @@ class ProxyExecContext : public ExecContext
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Status status() const { return actualXC->status(); }
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Status status() const { return actualXC->status(); }
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void setStatus(Status new_status) { actualXC->setStatus(new_status); }
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/// Set the status to Active. Optional delay indicates number of
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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/// cycles to wait before beginning execution.
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void activate(int delay = 1) { actualXC->activate(delay); }
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void activate(int delay = 1) { actualXC->activate(delay); }
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void unserialize(Checkpoint *cp, const std::string §ion)
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void unserialize(Checkpoint *cp, const std::string §ion)
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{ actualXC->unserialize(cp, section); }
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{ actualXC->unserialize(cp, section); }
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#if FULL_SYSTEM
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Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
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Tick readLastActivate() { return actualXC->readLastActivate(); }
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Tick readLastSuspend() { return actualXC->readLastSuspend(); }
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#endif
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int getThreadNum() { return actualXC->getThreadNum(); }
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int getThreadNum() { return actualXC->getThreadNum(); }
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bool validInstAddr(Addr addr) { return actualXC->validInstAddr(addr); }
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bool validInstAddr(Addr addr) { return actualXC->validInstAddr(addr); }
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@ -365,21 +382,11 @@ class ProxyExecContext : public ExecContext
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bool inPalMode() { return actualXC->inPalMode(); }
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bool inPalMode() { return actualXC->inPalMode(); }
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void ev5_trap(Fault fault) { actualXC->ev5_trap(fault); }
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bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
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bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
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#endif
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#endif
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// @todo: Fix this!
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// @todo: Fix this!
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bool misspeculating() { return false; }
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bool misspeculating() { return actualXC->misspeculating(); }
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/** Meant to be more generic trap function to be
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* called when an instruction faults.
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* @param fault The fault generated by executing the instruction.
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* @todo How to do this properly so it's dependent upon ISA only?
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*/
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void trap(Fault fault) { actualXC->trap(fault); }
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
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IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
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@ -30,6 +30,7 @@
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#include <vector>
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#include <vector>
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/intr_control.hh"
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#include "cpu/intr_control.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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#include "sim/sim_object.hh"
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|
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@ -32,6 +32,7 @@
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#include "base/callback.hh"
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#include "base/callback.hh"
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#include "base/statistics.hh"
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#include "base/statistics.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exec_context.hh"
|
||||||
#include "cpu/profile.hh"
|
#include "cpu/profile.hh"
|
||||||
|
|
|
@ -35,6 +35,8 @@
|
||||||
#include "sim/host.hh"
|
#include "sim/host.hh"
|
||||||
#include "arch/stacktrace.hh"
|
#include "arch/stacktrace.hh"
|
||||||
|
|
||||||
|
class ExecContext;
|
||||||
|
|
||||||
class ProfileNode
|
class ProfileNode
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
|
|
|
@ -766,7 +766,7 @@ SimpleCPU::tick()
|
||||||
|
|
||||||
// decode the instruction
|
// decode the instruction
|
||||||
inst = gtoh(inst);
|
inst = gtoh(inst);
|
||||||
curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC()));
|
curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
|
||||||
|
|
||||||
traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
|
traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
|
||||||
cpuXC->readPC());
|
cpuXC->readPC());
|
||||||
|
|
|
@ -42,6 +42,7 @@
|
||||||
#include "mem/bus/pio_interface.hh"
|
#include "mem/bus/pio_interface.hh"
|
||||||
#include "mem/bus/pio_interface_impl.hh"
|
#include "mem/bus/pio_interface_impl.hh"
|
||||||
#include "mem/functional/memory_control.hh"
|
#include "mem/functional/memory_control.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
#include "cpu/intr_control.hh"
|
#include "cpu/intr_control.hh"
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
#include "sim/system.hh"
|
#include "sim/system.hh"
|
||||||
|
|
|
@ -35,6 +35,7 @@
|
||||||
#include "cpu/exec_context.hh"
|
#include "cpu/exec_context.hh"
|
||||||
#include "kern/kernel_stats.hh"
|
#include "kern/kernel_stats.hh"
|
||||||
#include "kern/tru64/tru64_syscalls.hh"
|
#include "kern/tru64/tru64_syscalls.hh"
|
||||||
|
#include "sim/system.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
using namespace Stats;
|
using namespace Stats;
|
||||||
|
|
|
@ -32,6 +32,7 @@
|
||||||
#include "kern/linux/events.hh"
|
#include "kern/linux/events.hh"
|
||||||
#include "kern/linux/printk.hh"
|
#include "kern/linux/printk.hh"
|
||||||
#include "kern/system_events.hh"
|
#include "kern/system_events.hh"
|
||||||
|
#include "sim/system.hh"
|
||||||
|
|
||||||
|
|
||||||
namespace Linux {
|
namespace Linux {
|
||||||
|
@ -41,7 +42,7 @@ DebugPrintkEvent::process(ExecContext *xc)
|
||||||
{
|
{
|
||||||
if (DTRACE(DebugPrintf)) {
|
if (DTRACE(DebugPrintf)) {
|
||||||
if (!raw) {
|
if (!raw) {
|
||||||
StringWrap name(xc->system->name() + ".dprintk");
|
StringWrap name(xc->getSystemPtr()->name() + ".dprintk");
|
||||||
DPRINTFN("");
|
DPRINTFN("");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -31,9 +31,11 @@
|
||||||
|
|
||||||
#include "base/cprintf.hh"
|
#include "base/cprintf.hh"
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
|
#include "base/loader/symtab.hh"
|
||||||
#include "cpu/exec_context.hh"
|
#include "cpu/exec_context.hh"
|
||||||
#include "kern/tru64/mbuf.hh"
|
#include "kern/tru64/mbuf.hh"
|
||||||
#include "sim/host.hh"
|
#include "sim/host.hh"
|
||||||
|
#include "sim/system.hh"
|
||||||
#include "arch/arguments.hh"
|
#include "arch/arguments.hh"
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
#include "arch/vtophys.hh"
|
#include "arch/vtophys.hh"
|
||||||
|
|
|
@ -35,6 +35,7 @@
|
||||||
#include "mem/functional/memory_control.hh"
|
#include "mem/functional/memory_control.hh"
|
||||||
#include "arch/arguments.hh"
|
#include "arch/arguments.hh"
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
|
#include "sim/system.hh"
|
||||||
|
|
||||||
using namespace TheISA;
|
using namespace TheISA;
|
||||||
|
|
||||||
|
|
|
@ -83,13 +83,15 @@ namespace AlphaPseudo
|
||||||
if (!doQuiesce || ns == 0)
|
if (!doQuiesce || ns == 0)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if (xc->quiesceEvent.scheduled())
|
Event *quiesceEvent = xc->getQuiesceEvent();
|
||||||
xc->quiesceEvent.reschedule(curTick + Clock::Int::ns * ns);
|
|
||||||
|
if (quiesceEvent->scheduled())
|
||||||
|
quiesceEvent->reschedule(curTick + Clock::Int::ns * ns);
|
||||||
else
|
else
|
||||||
xc->quiesceEvent.schedule(curTick + Clock::Int::ns * ns);
|
quiesceEvent->schedule(curTick + Clock::Int::ns * ns);
|
||||||
|
|
||||||
xc->suspend();
|
xc->suspend();
|
||||||
xc->kernelStats->quiesce();
|
xc->getCpuPtr()->kernelStats->quiesce();
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -98,19 +100,23 @@ namespace AlphaPseudo
|
||||||
if (!doQuiesce || cycles == 0)
|
if (!doQuiesce || cycles == 0)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if (xc->quiesceEvent.scheduled())
|
Event *quiesceEvent = xc->getQuiesceEvent();
|
||||||
xc->quiesceEvent.reschedule(curTick + xc->cpu->cycles(cycles));
|
|
||||||
|
if (quiesceEvent->scheduled())
|
||||||
|
quiesceEvent->reschedule(curTick +
|
||||||
|
xc->getCpuPtr()->cycles(cycles));
|
||||||
else
|
else
|
||||||
xc->quiesceEvent.schedule(curTick + xc->cpu->cycles(cycles));
|
quiesceEvent->schedule(curTick +
|
||||||
|
xc->getCpuPtr()->cycles(cycles));
|
||||||
|
|
||||||
xc->suspend();
|
xc->suspend();
|
||||||
xc->kernelStats->quiesce();
|
xc->getCpuPtr()->kernelStats->quiesce();
|
||||||
}
|
}
|
||||||
|
|
||||||
uint64_t
|
uint64_t
|
||||||
quiesceTime(ExecContext *xc)
|
quiesceTime(ExecContext *xc)
|
||||||
{
|
{
|
||||||
return (xc->lastActivate - xc->lastSuspend) / Clock::Int::ns ;
|
return (xc->readLastActivate() - xc->readLastSuspend()) / Clock::Int::ns;
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
|
Loading…
Reference in a new issue