X86: Add L1 caches for the TLB walkers.

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
This commit is contained in:
Gabe Black 2011-02-01 18:28:41 -08:00
parent 4b4cd0303e
commit 119f5f8e94
4 changed files with 29 additions and 9 deletions

View file

@ -43,6 +43,12 @@ def config_cache(options, system):
for i in xrange(options.num_cpus): for i in xrange(options.num_cpus):
if options.caches: if options.caches:
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'),
PageTableWalkerCache(),
PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB')) L1Cache(size = '64kB'))
if options.l2cache: if options.l2cache:

View file

@ -42,6 +42,14 @@ class L2Cache(BaseCache):
mshrs = 20 mshrs = 20
tgts_per_mshr = 12 tgts_per_mshr = 12
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
latency = '1ns'
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
class IOCache(BaseCache): class IOCache(BaseCache):
assoc = 8 assoc = 8
block_size = 64 block_size = 64

View file

@ -166,7 +166,7 @@ class BaseCPU(MemObject):
if p != 'physmem_port': if p != 'physmem_port':
exec('self.%s = bus.port' % p) exec('self.%s = bus.port' % p)
def addPrivateSplitL1Caches(self, ic, dc): def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
assert(len(self._mem_ports) < 8) assert(len(self._mem_ports) < 8)
self.icache = ic self.icache = ic
self.dcache = dc self.dcache = dc
@ -174,13 +174,19 @@ class BaseCPU(MemObject):
self.dcache_port = dc.cpu_side self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['FULL_SYSTEM']: if buildEnv['FULL_SYSTEM']:
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
if buildEnv['TARGET_ISA'] == 'x86': if buildEnv['TARGET_ISA'] == 'x86':
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.itb.walker.port = iwc.cpu_side
self.dtb.walker.port = dwc.cpu_side
self._mem_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
self._mem_ports += ["interrupts.pio", "interrupts.int_port"] self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
elif buildEnv['TARGET_ISA'] == 'arm':
self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c): def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc) self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
self.toL2Bus = Bus() self.toL2Bus = Bus()
self.connectMemPorts(self.toL2Bus) self.connectMemPorts(self.toL2Bus)
self.l2cache = l2c self.l2cache = l2c

View file

@ -141,7 +141,7 @@ class DerivO3CPU(BaseCPU):
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
def addPrivateSplitL1Caches(self, ic, dc): def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
BaseCPU.addPrivateSplitL1Caches(self, ic, dc) BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
self.icache.tgts_per_mshr = 20 self.icache.tgts_per_mshr = 20
self.dcache.tgts_per_mshr = 20 self.dcache.tgts_per_mshr = 20