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Panic if any CMT registers are accessed

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src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add CMT ASI registers
src/arch/sparc/tlb.cc:
    Panic if any of the CMT registers are being accessed

--HG--
extra : convert_revision : b9a94281e2074a576ac21d042b756950d509e758
This commit is contained in:
Ali Saidi 2007-03-08 21:49:13 -05:00
parent 027dfa01e6
commit 1158da37fb
3 changed files with 8 additions and 2 deletions
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6
src/arch/sparc/asi.cc
View file

@ -247,7 +247,8 @@ namespace SparcISA
bool AsiIsCmt(ASI asi) bool AsiIsCmt(ASI asi)
{ {
return return
(asi == ASI_CMT_PER_STRAND); (asi == ASI_CMT_PER_STRAND) ||
(asi == ASI_CMT_SHARED);
} }
bool AsiIsQueue(ASI asi) bool AsiIsQueue(ASI asi)
@ -295,7 +296,8 @@ namespace SparcISA
bool AsiIsReg(ASI asi) bool AsiIsReg(ASI asi)
{ {
return AsiIsMmu(asi) || AsiIsScratchPad(asi) || return AsiIsMmu(asi) || AsiIsScratchPad(asi) ||
AsiIsSparcError(asi) || AsiIsInterrupt(asi); AsiIsSparcError(asi) || AsiIsInterrupt(asi)
|| AsiIsCmt(asi);
} }
bool AsiIsSparcError(ASI asi) bool AsiIsSparcError(ASI asi)

1
src/arch/sparc/asi.hh
View file

@ -115,6 +115,7 @@ namespace SparcISA
ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E, ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E,
ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F, ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
ASI_STREAM_MA = 0x40, ASI_STREAM_MA = 0x40,
ASI_CMT_SHARED = 0x41,
//0x41 implementation dependent //0x41 implementation dependent
ASI_SPARC_BIST_CONTROL = 0x42, ASI_SPARC_BIST_CONTROL = 0x42,
ASI_INST_MASK_REG = 0x42, ASI_INST_MASK_REG = 0x42,

3
src/arch/sparc/tlb.cc
View file

@ -693,6 +693,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if (AsiIsPartialStore(asi)) if (AsiIsPartialStore(asi))
panic("Partial Store ASIs not supported\n"); panic("Partial Store ASIs not supported\n");
if (AsiIsCmt(asi))
panic("Cmt ASI registers not implmented\n");
if (AsiIsInterrupt(asi)) if (AsiIsInterrupt(asi))
goto handleIntRegAccess; goto handleIntRegAccess;
if (AsiIsMmu(asi)) if (AsiIsMmu(asi))