move setStatus into the .cc file
--HG-- extra : convert_revision : 9ccf885274d72ea3151a0db76b580dd51763edab
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b6c77fe6f8
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0ff2457bfa
2 changed files with 58 additions and 55 deletions
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@ -212,6 +212,63 @@ SimpleCPU::execCtxStatusChg(int thread_num) {
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setStatus(Idle);
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}
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void
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SimpleCPU::setStatus(Status new_status)
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{
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Status old_status = status();
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// We should never even get here if the CPU has been switched out.
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assert(old_status != SwitchedOut);
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_status = new_status;
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switch (status()) {
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case IcacheMissStall:
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assert(old_status == Running);
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lastIcacheStall = curTick;
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if (tickEvent.scheduled())
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tickEvent.squash();
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break;
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case IcacheMissComplete:
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assert(old_status == IcacheMissStall);
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + 1);
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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break;
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case DcacheMissStall:
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assert(old_status == Running);
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lastDcacheStall = curTick;
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if (tickEvent.scheduled())
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tickEvent.squash();
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break;
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case Idle:
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assert(old_status == Running);
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idleFraction++;
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if (tickEvent.scheduled())
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tickEvent.squash();
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break;
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case Running:
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assert(old_status == Idle ||
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old_status == DcacheMissStall ||
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old_status == IcacheMissComplete);
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if (old_status == Idle && curTick != 0)
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idleFraction--;
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + 1);
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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break;
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default:
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panic("can't get here");
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}
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}
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void
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SimpleCPU::regStats()
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@ -174,61 +174,7 @@ class SimpleCPU : public BaseCPU
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virtual void execCtxStatusChg(int thread_num);
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void setStatus(Status new_status) {
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Status old_status = status();
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// We should never even get here if the CPU has been switched out.
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assert(old_status != SwitchedOut);
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_status = new_status;
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switch (status()) {
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case IcacheMissStall:
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assert(old_status == Running);
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lastIcacheStall = curTick;
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if (tickEvent.scheduled())
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tickEvent.squash();
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break;
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case IcacheMissComplete:
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assert(old_status == IcacheMissStall);
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + 1);
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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break;
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case DcacheMissStall:
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assert(old_status == Running);
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lastDcacheStall = curTick;
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if (tickEvent.scheduled())
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tickEvent.squash();
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break;
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case Idle:
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assert(old_status == Running);
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idleFraction++;
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if (tickEvent.scheduled())
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tickEvent.squash();
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break;
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case Running:
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assert(old_status == Idle ||
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old_status == DcacheMissStall ||
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old_status == IcacheMissComplete);
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if (old_status == Idle && curTick != 0)
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idleFraction--;
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + 1);
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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break;
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default:
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panic("can't get here");
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}
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}
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void setStatus(Status new_status);
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// statistics
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virtual void regStats();
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