Fix checker to work in newmem in SE mode.
src/cpu/o3/fetch_impl.hh: Give the checker a pointer to the icachePort. src/cpu/o3/lsq_unit_impl.hh: Give the checker a pointer to the dcachePort. src/mem/request.hh: Allow checking for the scResult being valid prior to accessing it. --HG-- extra : convert_revision : ced4180588d242111ecba4a11586823badd6cf15
This commit is contained in:
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090496bf2d
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0f014e4340
5 changed files with 99 additions and 36 deletions
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@ -64,8 +64,7 @@ CheckerCPU::init()
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CheckerCPU::CheckerCPU(Params *p)
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: BaseCPU(p), cpuXC(NULL), xcProxy(NULL)
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{
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memReq = new Request();
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// memReq->data = new uint8_t[64];
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memReq = NULL;
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numInst = 0;
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startNumInst = 0;
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@ -81,6 +80,8 @@ CheckerCPU::CheckerCPU(Params *p)
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dtb = p->dtb;
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systemPtr = NULL;
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memPtr = NULL;
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#else
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process = p->process;
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#endif
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}
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@ -93,7 +94,7 @@ CheckerCPU::setMemory(MemObject *mem)
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{
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memPtr = mem;
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#if !FULL_SYSTEM
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cpuXC = new CPUExecContext(this, /* thread_num */ 0, NULL,
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cpuXC = new CPUExecContext(this, /* thread_num */ 0, process,
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/* asid */ 0, mem);
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cpuXC->setStatus(ExecContext::Suspended);
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@ -132,6 +133,18 @@ CheckerCPU::setSystem(System *system)
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}
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#endif
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void
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CheckerCPU::setIcachePort(Port *icache_port)
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{
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icachePort = icache_port;
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}
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void
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CheckerCPU::setDcachePort(Port *dcache_port)
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{
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dcachePort = dcache_port;
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}
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void
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CheckerCPU::serialize(ostream &os)
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{
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@ -170,25 +183,28 @@ template <class T>
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Fault
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CheckerCPU::read(Addr addr, T &data, unsigned flags)
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{
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/*
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memReq->reset(addr, sizeof(T), flags);
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// need to fill in CPU & thread IDs here
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memReq = new Request();
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memReq->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
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// translate to physical address
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translateDataReadReq(memReq);
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
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if (!(memReq->flags & UNCACHEABLE)) {
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pkt->dataStatic(&data);
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if (!(memReq->getFlags() & UNCACHEABLE)) {
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// Access memory to see if we have the same data
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cpuXC->read(memReq, data);
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dcachePort->sendFunctional(pkt);
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} else {
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// Assume the data is correct if it's an uncached access
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memcpy(&data, &unverifiedResult.integer, sizeof(T));
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}
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*/
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delete pkt;
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return NoFault;
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}
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@ -237,8 +253,10 @@ template <class T>
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Fault
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CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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/*
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memReq->reset(addr, sizeof(T), flags);
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// need to fill in CPU & thread IDs here
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memReq = new Request();
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memReq->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
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// translate to physical address
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cpuXC->translateDataWriteReq(memReq);
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@ -253,19 +271,21 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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// This is because the LSQ would have to be snooped in the CPU to
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// verify this data.
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if (unverifiedReq &&
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!(unverifiedReq->flags & UNCACHEABLE) &&
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(!(unverifiedReq->flags & LOCKED) ||
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((unverifiedReq->flags & LOCKED) &&
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unverifiedReq->result == 1))) {
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#if 0
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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cpuXC->read(memReq, inst_data);
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#endif
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!(unverifiedReq->getFlags() & UNCACHEABLE) &&
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(!(unverifiedReq->getFlags() & LOCKED) ||
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((unverifiedReq->getFlags() & LOCKED) &&
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unverifiedReq->getScResult() == 1))) {
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T inst_data;
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memcpy(&inst_data, unverifiedReq->data, sizeof(T));
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/*
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// This code would work if the LSQ allowed for snooping.
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Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
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pkt.dataStatic(&inst_data);
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dcachePort->sendFunctional(pkt);
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delete pkt;
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*/
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memcpy(&inst_data, unverifiedMemData, sizeof(T));
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if (data != inst_data) {
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warn("%lli: Store value does not match value in memory! "
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@ -278,9 +298,9 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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// Assume the result was the same as the one passed in. This checker
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// doesn't check if the SC should succeed or fail, it just checks the
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// value.
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if (res)
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*res = unverifiedReq->result;
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*/
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if (res && unverifiedReq->scResultValid())
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*res = unverifiedReq->getScResult();
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return NoFault;
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}
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@ -451,6 +471,7 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
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inst->seqNum, inst->readPC());
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unverifiedResult.integer = inst->readIntResult();
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unverifiedReq = inst->req;
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unverifiedMemData = inst->memData;
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numCycles++;
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Fault fault = NoFault;
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@ -494,10 +515,13 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
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#define IFETCH_FLAGS(pc) 0
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#endif
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uint64_t fetch_PC = cpuXC->readPC() & ~3;
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// set up memory request for instruction fetch
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// memReq->cmd = Read;
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// memReq->reset(cpuXC->readPC() & ~3, sizeof(uint32_t),
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// IFETCH_FLAGS(cpuXC->readPC()));
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memReq = new Request(inst->threadNumber, fetch_PC,
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sizeof(uint32_t),
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IFETCH_FLAGS(cpuXC->readPC()),
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fetch_PC, cpuXC->readCpuId(), inst->threadNumber);
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bool succeeded = translateInstReq(memReq);
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@ -526,7 +550,14 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
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}
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if (fault == NoFault) {
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// cpuXC->read(memReq, machInst);
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Packet *pkt = new Packet(memReq, Packet::ReadReq,
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Packet::Broadcast);
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pkt->dataStatic(&machInst);
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icachePort->sendFunctional(pkt);
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delete pkt;
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// keep an instruction count
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numInst++;
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@ -547,6 +578,10 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
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fault = inst->getFault();
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}
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// Discard fetch's memReq.
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delete memReq;
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memReq = NULL;
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// Either the instruction was a fault and we should process the fault,
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// or we should just go ahead execute the instruction. This assumes
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// that the instruction is properly marked as a fault.
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@ -609,6 +644,11 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
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// that have been modified).
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validateState();
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if (memReq) {
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delete memReq;
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memReq = NULL;
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}
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// Continue verifying instructions if there's another completed
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// instruction waiting to be verified.
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if (instList.empty()) {
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@ -679,7 +719,7 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
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cpuXC->setMiscReg(idx, inst->readIntResult());
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}
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} else if (result.integer != inst->readIntResult()) {
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warn("%lli: Instruction results do not match! (Results may not "
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warn("%lli: Instruction results do not match! (Values may not "
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"actually be integers) Inst: %#x, checker: %#x",
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curTick, inst->readIntResult(), result.integer);
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handleError();
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@ -108,6 +108,8 @@ class CheckerCPU : public BaseCPU
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CheckerCPU(Params *p);
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virtual ~CheckerCPU();
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Process *process;
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void setMemory(MemObject *mem);
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MemObject *memPtr;
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@ -117,6 +119,15 @@ class CheckerCPU : public BaseCPU
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System *systemPtr;
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#endif
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void setIcachePort(Port *icache_port);
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Port *icachePort;
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void setDcachePort(Port *dcache_port);
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Port *dcachePort;
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public:
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// execution context
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CPUExecContext *cpuXC;
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@ -141,8 +152,8 @@ class CheckerCPU : public BaseCPU
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// current instruction
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MachInst machInst;
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// Refcounted pointer to the one memory request.
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Request *memReq;
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// Pointer to the one memory request.
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RequestPtr memReq;
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StaticInstPtr curStaticInst;
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@ -334,6 +345,7 @@ class CheckerCPU : public BaseCPU
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Result unverifiedResult;
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Request *unverifiedReq;
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uint8_t *unverifiedMemData;
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bool changedPC;
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bool willChangePC;
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@ -30,6 +30,7 @@
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#include "arch/isa_traits.hh"
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#include "arch/utility.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/o3/fetch.hh"
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#include "mem/packet.hh"
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@ -289,6 +290,10 @@ DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
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icachePort->setPeer(mem_dport);
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mem_dport->setPeer(icachePort);
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if (cpu->checker) {
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cpu->checker->setIcachePort(icachePort);
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}
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// Fetch needs to start fetching instructions at the very beginning,
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// so it must start up in active state.
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switchToActive();
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@ -186,6 +186,10 @@ LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
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Port *mem_dport = mem->getPort("");
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dcachePort->setPeer(mem_dport);
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mem_dport->setPeer(dcachePort);
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if (cpu->checker) {
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cpu->checker->setDcachePort(dcachePort);
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}
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}
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template<class Impl>
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@ -208,6 +208,8 @@ class Request
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/** Accessor function for asid.*/
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int getAsid() { assert(validAsidVaddr); return asid; }
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/** Accessor function to check if sc result is valid. */
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bool scResultValid() { return validScResult; }
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/** Accessor function for store conditional return value.*/
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uint64_t getScResult() { assert(validScResult); return scResult; }
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/** Accessor function for store conditional return value.*/
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