configs/inorder: add options for switch-on-miss to inorder cpu

src/cpu/inorder/InOrderCPU.py

@@ -30,10 +30,15 @@ from m5.params import *
 from m5.proxy import *
 from BaseCPU import BaseCPU
 
+class ThreadModel(Enum):
+    vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
+
 class InOrderCPU(BaseCPU):
     type = 'InOrderCPU'
     activity = Param.Unsigned(0, "Initial count")
 
+    threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
+    
     cachePorts = Param.Unsigned(2, "Cache Ports")
     stageWidth = Param.Unsigned(1, "Stage width")
 

src/cpu/inorder/cpu.cc

@@ -216,6 +216,15 @@ InOrderCPU::InOrderCPU(Params *params)
               "in your InOrder implementation or "
               "edit your workload size.");
     }
+
+    if (active_threads > 1) {
+        threadModel = (InOrderCPU::ThreadModel) params->threadModel;
+    } else {
+        threadModel = Single;
+    }
+     
+        
+    
 #endif
 
     // Bind the fetch & data ports from the resource pool.

src/cpu/inorder/cpu.hh

@@ -100,6 +100,15 @@ class InOrderCPU : public BaseCPU
     /** Type of core that this is */
     std::string coreType;
 
+    // Only need for SE MODE
+    enum ThreadModel {
+        Single,
+        SMT,
+        SwitchOnCacheMiss
+    };
+    
+    ThreadModel threadModel;
+
     int readCpuId() { return cpu_id; }
 
     void setCpuId(int val) { cpu_id = val; }
@@ -117,7 +126,6 @@ class InOrderCPU : public BaseCPU
 
     /** Overall CPU status. */
     Status _status;
-
   private:
     /** Define TickEvent for the CPU */
     class TickEvent : public Event